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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-05-14 13:56:44 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-05-17 15:27:15 -0700 |
| commit | 0218a16e540ad416683e19dfbd52f75092507b27 (patch) | |
| tree | 709a16801b296fa5a508c2ce923ab44f0ffe7e74 /COPYING.PYTHON | |
| parent | 3bd2dec1a1e8fadb49e3ff2e2633f79e01a25c41 (diff) | |
fpu/softfloat: Define floatN_default_nan in terms of parts_default_nan
Isolate the target-specific choice to 2 functions instead of 6.
The code in float16_default_nan was only correct for ARM, MIPS, and X86.
Though float16 support is rare among our targets.
The code in float128_default_nan was arguably wrong for Sparc. While
QEMU supports the Sparc 128-bit insns, no real cpu enables it.
The code in floatx80_default_nan tried to be over-general. There are
only two targets that support this format: x86 and m68k. Thus there
is no point in inventing a value for snan_bit_is_one.
Move routines that no longer have ifdefs out of softfloat-specialize.h.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'COPYING.PYTHON')
0 files changed, 0 insertions, 0 deletions