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authorPeter Maydell <peter.maydell@linaro.org>2022-11-24 11:50:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-12-16 15:58:15 +0000
commit9130cade5fc22d11eb05493737439918f501b752 (patch)
tree533a563464d46b3f81e163ff93b9825d11b6d126
parent3b750f1b1aa6b6835853badddee6613515ab0530 (diff)
target/arm: Convert to 3-phase reset
Convert the Arm CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20221124115023.2437291-3-peter.maydell@linaro.org
-rw-r--r--target/arm/cpu-qom.h4
-rw-r--r--target/arm/cpu.c13
2 files changed, 11 insertions, 6 deletions
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 64c44cef2d..514c22ced9 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
/**
* ARMCPUClass:
* @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* An ARM CPU model.
*/
@@ -54,7 +54,7 @@ struct ARMCPUClass {
const ARMCPUInfo *info;
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
};
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0f55004d7e..2fa022f62b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
assert(oldvalue == newvalue);
}
-static void arm_cpu_reset(DeviceState *dev)
+static void arm_cpu_reset_hold(Object *obj)
{
- CPUState *s = CPU(dev);
+ CPUState *s = CPU(obj);
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
- acc->parent_reset(dev);
+ if (acc->parent_phases.hold) {
+ acc->parent_phases.hold(obj);
+ }
memset(env, 0, offsetof(CPUARMState, end_reset_fields));
@@ -2211,12 +2213,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(acc);
DeviceClass *dc = DEVICE_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
device_class_set_props(dc, arm_cpu_properties);
- device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
+
+ resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
+ &acc->parent_phases);
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;