aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPhilippe Mathieu-Daudé <philmd@linaro.org>2024-08-13 17:22:37 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-08-20 00:38:48 +0200
commit44017c66556da85168d31380ca36f0311d37a1a8 (patch)
tree2c1850c7153fddc1823450bb8fdcf275c5e6bcf4
parent7ce9760d64e8a884f044f95a1f32f96c2e0fafa0 (diff)
target/mips: Load PTE as DATA
PTE is not CODE so load it as normal DATA access. Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240814090452.2591-4-philmd@linaro.org>
-rw-r--r--target/mips/tcg/sysemu/tlb_helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 0e94e00a5f..3836137750 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -603,9 +603,9 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op,
oi = make_memop_idx(op | MO_TE, ptw_mmu_idx);
if (op == MO_64) {
- *pte = cpu_ldq_code_mmu(env, vaddr, oi, 0);
+ *pte = cpu_ldq_mmu(env, vaddr, oi, 0);
} else {
- *pte = cpu_ldl_code_mmu(env, vaddr, oi, 0);
+ *pte = cpu_ldl_mmu(env, vaddr, oi, 0);
}
return true;