Convert rest of ops using float32 to TCG, remove FT0 and FT1

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162

5 files changed, 39 insertions, 64 deletions

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index e24031a680..42df2a7df5 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -303,7 +303,6 @@ typedef struct CPUSPARCState {
     uint64_t prom_addr;
 #endif
     /* temporary float registers */
-    float32 ft0, ft1;
     float64 dt0, dt1;
     float128 qt0, qt1;
     float_status fp_status;
diff --git a/target-sparc/exec.h b/target-sparc/exec.h
index dbfcc35147..35dcb475ef 100644
--- a/target-sparc/exec.h
+++ b/target-sparc/exec.h
@@ -5,8 +5,6 @@
 
 register struct CPUSPARCState *env asm(AREG0);
 
-#define FT0 (env->ft0)
-#define FT1 (env->ft1)
 #define DT0 (env->dt0)
 #define DT1 (env->dt1)
 #define QT0 (env->qt0)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 7dc654780d..adef1f292e 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -93,10 +93,6 @@ DEF_HELPER(void, helper_fcmpeq_fcc3, (void))
 #endif
 DEF_HELPER(void, raise_exception, (int tt))
 #define F_HELPER_0_0(name) DEF_HELPER(void, helper_f ## name, (void))
-#define F_HELPER_SDQ_0_0(name)                  \
-    F_HELPER_0_0(name ## s);                    \
-    F_HELPER_0_0(name ## d);                    \
-    F_HELPER_0_0(name ## q)
 #define F_HELPER_DQ_0_0(name)                   \
     F_HELPER_0_0(name ## d);                    \
     F_HELPER_0_0(name ## q)
@@ -111,11 +107,11 @@ DEF_HELPER(float32, helper_fsubs, (float32 src1, float32 src2))
 DEF_HELPER(float32, helper_fmuls, (float32 src1, float32 src2))
 DEF_HELPER(float32, helper_fdivs, (float32 src1, float32 src2))
 
-F_HELPER_0_0(smuld);
+DEF_HELPER(void, helper_fsmuld, (float32 src1, float32 src2))
 F_HELPER_0_0(dmulq);
 
 DEF_HELPER(float32, helper_fnegs, (float32 src))
-F_HELPER_0_0(itod);
+DEF_HELPER(void, helper_fitod, (int32_t src))
 DEF_HELPER(void, helper_fitoq, (int32_t src))
 
 DEF_HELPER(float32, helper_fitos, (int32_t src))
@@ -123,19 +119,20 @@ DEF_HELPER(float32, helper_fitos, (int32_t src))
 #ifdef TARGET_SPARC64
 DEF_HELPER(void, helper_fnegd, (void))
 DEF_HELPER(void, helper_fnegq, (void))
-F_HELPER_SDQ_0_0(xto);
+DEF_HELPER(uint32_t, helper_fxtos, (void))
+F_HELPER_DQ_0_0(xto);
 #endif
-F_HELPER_0_0(dtos);
-F_HELPER_0_0(stod);
+DEF_HELPER(float32, helper_fdtos, (void))
+DEF_HELPER(void, helper_fstod, (float32 src))
 DEF_HELPER(float32, helper_fqtos, (void))
 DEF_HELPER(void, helper_fstoq, (float32 src))
 F_HELPER_0_0(qtod);
 F_HELPER_0_0(dtoq);
 DEF_HELPER(int32_t, helper_fstoi, (float32 src))
-F_HELPER_0_0(dtoi);
+DEF_HELPER(int32_t, helper_fdtoi, (void))
 DEF_HELPER(int32_t, helper_fqtoi, (void))
 #ifdef TARGET_SPARC64
-F_HELPER_0_0(stox);
+DEF_HELPER(void, helper_fstox, (uint32_t src))
 F_HELPER_0_0(dtox);
 F_HELPER_0_0(qtox);
 F_HELPER_0_0(aligndata);
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 1cafa6723f..9bd0d65b49 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -106,10 +106,10 @@ F_BINOP(mul);
 F_BINOP(div);
 #undef F_BINOP
 
-void helper_fsmuld(void)
+void helper_fsmuld(float32 src1, float32 src2)
 {
-    DT0 = float64_mul(float32_to_float64(FT0, &env->fp_status),
-                      float32_to_float64(FT1, &env->fp_status),
+    DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
+                      float32_to_float64(src2, &env->fp_status),
                       &env->fp_status);
 }
 
@@ -143,9 +143,9 @@ float32 helper_fitos(int32_t src)
     return int32_to_float32(src, &env->fp_status);
 }
 
-F_HELPER(ito, d)
+void helper_fitod(int32_t src)
 {
-    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
+    DT0 = int32_to_float64(src, &env->fp_status);
 }
 
 void helper_fitoq(int32_t src)
@@ -154,9 +154,9 @@ void helper_fitoq(int32_t src)
 }
 
 #ifdef TARGET_SPARC64
-F_HELPER(xto, s)
+float32 helper_fxtos(void)
 {
-    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
+    return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
 }
 
 F_HELPER(xto, d)
@@ -172,14 +172,14 @@ F_HELPER(xto, q)
 #undef F_HELPER
 
 /* floating point conversion */
-void helper_fdtos(void)
+float32 helper_fdtos(void)
 {
-    FT0 = float64_to_float32(DT1, &env->fp_status);
+    return float64_to_float32(DT1, &env->fp_status);
 }
 
-void helper_fstod(void)
+void helper_fstod(float32 src)
 {
-    DT0 = float32_to_float64(FT1, &env->fp_status);
+    DT0 = float32_to_float64(src, &env->fp_status);
 }
 
 float32 helper_fqtos(void)
@@ -208,9 +208,9 @@ int32_t helper_fstoi(float32 src)
     return float32_to_int32_round_to_zero(src, &env->fp_status);
 }
 
-void helper_fdtoi(void)
+int32_t helper_fdtoi(void)
 {
-    *((int32_t *)&FT0) = float64_to_int32_round_to_zero(DT1, &env->fp_status);
+    return float64_to_int32_round_to_zero(DT1, &env->fp_status);
 }
 
 int32_t helper_fqtoi(void)
@@ -219,9 +219,9 @@ int32_t helper_fqtoi(void)
 }
 
 #ifdef TARGET_SPARC64
-void helper_fstox(void)
+void helper_fstox(float32 src)
 {
-    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(FT1, &env->fp_status);
+    *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
 }
 
 void helper_fdtox(void)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 9e2c874b08..3d7d958b76 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -102,21 +102,6 @@ static int sign_extend(int x, int len)
 #define IS_IMM (insn & (1<<13))
 
 /* floating point registers moves */
-static void gen_op_load_fpr_FT0(unsigned int src)
-{
-    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft0));
-}
-
-static void gen_op_load_fpr_FT1(unsigned int src)
-{
-    tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, ft1));
-}
-
-static void gen_op_store_FT0_fpr(unsigned int dst)
-{
-    tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, ft0));
-}
-
 static void gen_op_load_fpr_DT0(unsigned int src)
 {
     tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
@@ -2475,12 +2460,11 @@ static void disas_sparc_insn(DisasContext * dc)
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         gen_op_store_QT0_fpr(QFPREG(rd));
                         break;
-                    case 0x69:
+                    case 0x69: /* fsmuld */
                         CHECK_FPU_FEATURE(dc, FSMULD);
-                        gen_op_load_fpr_FT0(rs1);
-                        gen_op_load_fpr_FT1(rs2);
                         gen_clear_float_exceptions();
-                        tcg_gen_helper_0_0(helper_fsmuld);
+                        tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1],
+                                           cpu_fpr[rs2]);
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         gen_op_store_DT0_fpr(DFPREG(rd));
                         break;
@@ -2500,12 +2484,12 @@ static void disas_sparc_insn(DisasContext * dc)
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
-                    case 0xc6:
+                    case 0xc6: /* fdtos */
                         gen_op_load_fpr_DT1(DFPREG(rs2));
                         gen_clear_float_exceptions();
-                        tcg_gen_helper_0_0(helper_fdtos);
+                        tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32);
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
-                        gen_op_store_FT0_fpr(rd);
+                        tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
                     case 0xc7: /* fqtos */
                         CHECK_FPU_FEATURE(dc, FLOAT128);
@@ -2515,14 +2499,12 @@ static void disas_sparc_insn(DisasContext * dc)
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
-                    case 0xc8:
-                        gen_op_load_fpr_FT1(rs2);
-                        tcg_gen_helper_0_0(helper_fitod);
+                    case 0xc8: /* fitod */
+                        tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]);
                         gen_op_store_DT0_fpr(DFPREG(rd));
                         break;
-                    case 0xc9:
-                        gen_op_load_fpr_FT1(rs2);
-                        tcg_gen_helper_0_0(helper_fstod);
+                    case 0xc9: /* fstod */
+                        tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]);
                         gen_op_store_DT0_fpr(DFPREG(rd));
                         break;
                     case 0xcb: /* fqtod */
@@ -2556,12 +2538,12 @@ static void disas_sparc_insn(DisasContext * dc)
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
-                    case 0xd2:
+                    case 0xd2: /* fdtoi */
                         gen_op_load_fpr_DT1(DFPREG(rs2));
                         gen_clear_float_exceptions();
-                        tcg_gen_helper_0_0(helper_fdtoi);
+                        tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32);
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
-                        gen_op_store_FT0_fpr(rd);
+                        tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
                     case 0xd3: /* fqtoi */
                         CHECK_FPU_FEATURE(dc, FLOAT128);
@@ -2612,9 +2594,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         gen_op_store_QT0_fpr(QFPREG(rd));
                         break;
                     case 0x81: /* V9 fstox */
-                        gen_op_load_fpr_FT1(rs2);
                         gen_clear_float_exceptions();
-                        tcg_gen_helper_0_0(helper_fstox);
+                        tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]);
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
                         gen_op_store_DT0_fpr(DFPREG(rd));
                         break;
@@ -2636,9 +2617,9 @@ static void disas_sparc_insn(DisasContext * dc)
                     case 0x84: /* V9 fxtos */
                         gen_op_load_fpr_DT1(DFPREG(rs2));
                         gen_clear_float_exceptions();
-                        tcg_gen_helper_0_0(helper_fxtos);
+                        tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32);
                         tcg_gen_helper_0_0(helper_check_ieee_exceptions);
-                        gen_op_store_FT0_fpr(rd);
+                        tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
                         break;
                     case 0x88: /* V9 fxtod */
                         gen_op_load_fpr_DT1(DFPREG(rs2));