diff options
| author | WANG Xuerui <git@xen0n.name> | 2021-12-21 13:40:47 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-12-21 13:17:06 -0800 |
| commit | 7257809f62d8e01b6e54046b3893c80a8fbfa1b4 (patch) | |
| tree | a63ce4a32787a9c3fb7a5d8bd6dc6371eb1a24b6 | |
| parent | 97b2fafbf707658e666cea85856148fb02e7628b (diff) | |
tcg/loongarch64: Implement deposit/extract ops
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-14-git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/loongarch64/tcg-target-con-set.h | 1 | ||||
| -rw-r--r-- | tcg/loongarch64/tcg-target.c.inc | 21 | ||||
| -rw-r--r-- | tcg/loongarch64/tcg-target.h | 8 |
3 files changed, 26 insertions, 4 deletions
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 9ac24b8ad0..d958183020 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -18,3 +18,4 @@ C_O0_I1(r) C_O1_I1(r, r) C_O1_I2(r, r, rC) C_O1_I2(r, r, rU) +C_O1_I2(r, 0, rZ) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index d9508d5295..9eba8f8146 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -531,6 +531,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_extract_i32: + tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); + break; + case INDEX_op_extract_i64: + tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); + break; + + case INDEX_op_deposit_i32: + tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_deposit_i64: + tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: default: @@ -560,6 +574,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_ext_i32_i64: case INDEX_op_not_i32: case INDEX_op_not_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: return C_O1_I1(r, r); case INDEX_op_andc_i32: @@ -584,6 +600,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* LoongArch reg-imm bitops have their imms ZERO-extended */ return C_O1_I2(r, r, rU); + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + /* Must deposit into the same register as input */ + return C_O1_I2(r, 0, rZ); + default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index cc9aecc681..1c9d0a9988 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -97,8 +97,8 @@ typedef enum { #define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_div2_i32 0 #define TCG_TARGET_HAS_rot_i32 0 -#define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_extract_i32 0 +#define TCG_TARGET_HAS_deposit_i32 1 +#define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_add2_i32 0 @@ -134,8 +134,8 @@ typedef enum { #define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_div2_i64 0 #define TCG_TARGET_HAS_rot_i64 0 -#define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_extract_i64 0 +#define TCG_TARGET_HAS_deposit_i64 1 +#define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_extrl_i64_i32 1 |