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authorBALATON Zoltan <balaton@eik.bme.hu>2024-07-22 00:55:06 +0200
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-07-23 20:30:36 +0200
commit53858a6a305248a567d441de12afc97d3dd9cc7d (patch)
tree8ecf371fced3f20b8a208880ff1bf8fd79cb1d84
parent16c84ec1bed94997d786671cc154c250375e2363 (diff)
hw/i2c/mpc_i2c: Fix mmio region size
The last register of this device is at offset 0x14 occupying 8 bits so to cover it the mmio region needs to be 0x15 bytes long. Also correct the name of the field storing this register value to match the register name. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Fixes: 7abb479c7a ("PPC: E500: Add FSL I2C controller") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240721225506.B32704E6039@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-rw-r--r--hw/i2c/mpc_i2c.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c
index cb051a520f..06d4ce7d68 100644
--- a/hw/i2c/mpc_i2c.c
+++ b/hw/i2c/mpc_i2c.c
@@ -82,7 +82,7 @@ struct MPCI2CState {
uint8_t cr;
uint8_t sr;
uint8_t dr;
- uint8_t dfssr;
+ uint8_t dfsrr;
};
static bool mpc_i2c_is_enabled(MPCI2CState *s)
@@ -293,7 +293,7 @@ static void mpc_i2c_write(void *opaque, hwaddr addr,
}
break;
case MPC_I2C_DFSRR:
- s->dfssr = value;
+ s->dfsrr = value;
break;
default:
DPRINTF("ERROR: Bad write addr 0x%x\n", (unsigned int)addr);
@@ -319,7 +319,7 @@ static const VMStateDescription mpc_i2c_vmstate = {
VMSTATE_UINT8(cr, MPCI2CState),
VMSTATE_UINT8(sr, MPCI2CState),
VMSTATE_UINT8(dr, MPCI2CState),
- VMSTATE_UINT8(dfssr, MPCI2CState),
+ VMSTATE_UINT8(dfsrr, MPCI2CState),
VMSTATE_END_OF_LIST()
}
};
@@ -329,7 +329,7 @@ static void mpc_i2c_realize(DeviceState *dev, Error **errp)
MPCI2CState *i2c = MPC_I2C(dev);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &i2c->irq);
memory_region_init_io(&i2c->iomem, OBJECT(i2c), &i2c_ops, i2c,
- "mpc-i2c", 0x14);
+ "mpc-i2c", 0x15);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &i2c->iomem);
i2c->bus = i2c_init_bus(dev, "i2c");
}