diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-22 17:31:14 +0100 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-10 19:39:41 +0300 |
| commit | d4c0ac705d720e19d9ec5b9fe1c6c7bb22b6913a (patch) | |
| tree | 695315434110c635a77046c0ef8b5d0cea8a838b | |
| parent | 09640031edd4314b8b2b05235f3da8114b4d5d36 (diff) | |
target/arm: Fix 64-bit SSRA
Typo applied byte-wise shift instead of double-word shift.
Cc: qemu-stable@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230821022025.397682-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit cd1e4db73646006039f25879af3bff55b2295ff3)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | target/arm/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 1e4d94e58a..e1fe68f73a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3063,7 +3063,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, .vece = MO_32 }, { .fni8 = gen_ssra64_i64, .fniv = gen_ssra_vec, - .fno = gen_helper_gvec_ssra_b, + .fno = gen_helper_gvec_ssra_d, .prefer_i64 = TCG_TARGET_REG_BITS == 64, .opt_opc = vecop_list, .load_dest = true, |