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authorJiayi Li <lijiayi@eswincomputing.com>2024-07-01 10:25:53 +0800
committerAlistair Francis <alistair.francis@wdc.com>2024-07-18 12:08:44 +1000
commit910c18a91738f9b77c5faf66e3534bb10d6e306e (patch)
tree77a376419aaa47fb317ec435da3b6cbff83e8806
parentae4bdcef6fd3166264a47ed6a17cb9870e32306e (diff)
target/riscv: Validate the mode in write_vstvec
Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li <lijiayi@eswincomputing.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240701022553.1982-1-lijiayi@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/csr.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 432c59dc66..f9229d92ab 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3791,7 +3791,12 @@ static RISCVException read_vstvec(CPURISCVState *env, int csrno,
static RISCVException write_vstvec(CPURISCVState *env, int csrno,
target_ulong val)
{
- env->vstvec = val;
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ if ((val & 3) < 2) {
+ env->vstvec = val;
+ } else {
+ qemu_log_mask(LOG_UNIMP, "CSR_VSTVEC: reserved mode not supported\n");
+ }
return RISCV_EXCP_NONE;
}