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authorRichard Henderson <richard.henderson@linaro.org>2020-08-18 11:26:59 -0700
committerRichard Henderson <richard.henderson@linaro.org>2020-09-01 07:41:38 -0700
commit8a42ddf013738a15c9cb739b9dfc07500cb27a21 (patch)
tree73adb6410b24c19f4e912ad777a6569034660869
parent853c93ed0d7d462224a6d74c474cf89981a2561b (diff)
target/microblaze: Tidy gdbstub
Use an enumeration for the gdb register mapping. Use one switch statement for the entire dispatch. Drop sreg_map and simply enumerate those cases explicitly. Force r0 to have value 0 and ignore writes. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--target/microblaze/gdbstub.c189
1 files changed, 99 insertions, 90 deletions
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 73e8973597..e65ec051a5 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -21,58 +21,80 @@
#include "cpu.h"
#include "exec/gdbstub.h"
+/*
+ * GDB expects SREGs in the following order:
+ * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
+ *
+ * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
+ * map them to anything and return a value of 0 instead.
+ */
+
+enum {
+ GDB_PC = 32 + 0,
+ GDB_MSR = 32 + 1,
+ GDB_EAR = 32 + 2,
+ GDB_ESR = 32 + 3,
+ GDB_FSR = 32 + 4,
+ GDB_BTR = 32 + 5,
+ GDB_PVR0 = 32 + 6,
+ GDB_PVR11 = 32 + 17,
+ GDB_EDR = 32 + 18,
+ GDB_SLR = 32 + 25,
+ GDB_SHR = 32 + 26,
+};
+
int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
CPUMBState *env = &cpu->env;
- /*
- * GDB expects SREGs in the following order:
- * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
- * They aren't stored in this order, so make a map.
- * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
- * map them to anything and return a value of 0 instead.
- */
- static const uint8_t sreg_map[6] = {
- SR_PC,
- SR_MSR,
- SR_EAR,
- SR_ESR,
- SR_FSR,
- SR_BTR
- };
+ uint32_t val;
- /*
- * GDB expects registers to be reported in this order:
- * R0-R31
- * PC-BTR
- * PVR0-PVR11
- * EDR-TLBHI
- * SLR-SHR
- */
- if (n < 32) {
- return gdb_get_reg32(mem_buf, env->regs[n]);
- } else {
- n -= 32;
- switch (n) {
- case 0 ... 5:
- return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]);
+ if (n > cc->gdb_num_core_regs) {
+ return 0;
+ }
+
+ switch (n) {
+ case 1 ... 31:
+ val = env->regs[n];
+ break;
+ case GDB_PC:
+ val = env->sregs[SR_PC];
+ break;
+ case GDB_MSR:
+ val = env->sregs[SR_MSR];
+ break;
+ case GDB_EAR:
+ val = env->sregs[SR_EAR];
+ break;
+ case GDB_ESR:
+ val = env->sregs[SR_ESR];
+ break;
+ case GDB_FSR:
+ val = env->sregs[SR_FSR];
+ break;
+ case GDB_BTR:
+ val = env->sregs[SR_BTR];
+ break;
+ case GDB_PVR0 ... GDB_PVR11:
/* PVR12 is intentionally skipped */
- case 6 ... 17:
- n -= 6;
- return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
- case 18:
- return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]);
+ val = env->pvr.regs[n - GDB_PVR0];
+ break;
+ case GDB_EDR:
+ val = env->sregs[SR_EDR];
+ break;
+ case GDB_SLR:
+ val = env->slr;
+ break;
+ case GDB_SHR:
+ val = env->shr;
+ break;
+ default:
/* Other SRegs aren't modeled, so report a value of 0 */
- case 19 ... 24:
- return gdb_get_reg32(mem_buf, 0);
- case 25:
- return gdb_get_reg32(mem_buf, env->slr);
- case 26:
- return gdb_get_reg32(mem_buf, env->shr);
- default:
- return 0;
- }
+ val = 0;
+ break;
}
+ return gdb_get_reg32(mem_buf, val);
}
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
@@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUMBState *env = &cpu->env;
uint32_t tmp;
- /*
- * GDB expects SREGs in the following order:
- * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
- * They aren't stored in this order, so make a map.
- * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
- * map them to anything.
- */
- static const uint8_t sreg_map[6] = {
- SR_PC,
- SR_MSR,
- SR_EAR,
- SR_ESR,
- SR_FSR,
- SR_BTR
- };
-
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
- /*
- * GDB expects registers to be reported in this order:
- * R0-R31
- * PC-BTR
- * PVR0-PVR11
- * EDR-TLBHI
- * SLR-SHR
- */
- if (n < 32) {
+ switch (n) {
+ case 1 ... 31:
env->regs[n] = tmp;
- } else {
- n -= 32;
- switch (n) {
- case 0 ... 5:
- env->sregs[sreg_map[n]] = tmp;
- break;
+ break;
+ case GDB_PC:
+ env->sregs[SR_PC] = tmp;
+ break;
+ case GDB_MSR:
+ env->sregs[SR_MSR] = tmp;
+ break;
+ case GDB_EAR:
+ env->sregs[SR_EAR] = tmp;
+ break;
+ case GDB_ESR:
+ env->sregs[SR_ESR] = tmp;
+ break;
+ case GDB_FSR:
+ env->sregs[SR_FSR] = tmp;
+ break;
+ case GDB_BTR:
+ env->sregs[SR_BTR] = tmp;
+ break;
+ case GDB_PVR0 ... GDB_PVR11:
/* PVR12 is intentionally skipped */
- case 6 ... 17:
- n -= 6;
- env->pvr.regs[n] = tmp;
- break;
- /* Only EDR is modeled in these indeces, so ignore the rest */
- case 18:
- env->sregs[SR_EDR] = tmp;
- break;
- case 25:
- env->slr = tmp;
- break;
- case 26:
- env->shr = tmp;
- break;
- }
+ env->pvr.regs[n - GDB_PVR0] = tmp;
+ break;
+ case GDB_EDR:
+ env->sregs[SR_EDR] = tmp;
+ break;
+ case GDB_SLR:
+ env->slr = tmp;
+ break;
+ case GDB_SHR:
+ env->shr = tmp;
+ break;
}
return 4;
}