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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-11-22 18:16:38 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-01-05 16:20:15 +0100
commitca1d323ca504e68af2c1b19dc99ec73054359507 (patch)
tree3c10e236c678d01eb905fb4b28bc0d1c50e00694
parentfa293f8125cbbcf147fdaed0873e40130cc75463 (diff)
hw/arm/bcm2836: Simplify use of 'reset-cbar' property
bcm2836_realize() is called by - bcm2836_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7") - bcm2837_class_init() which sets: bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53") Both Cortex-A7 / A53 have the ARM_FEATURE_CBAR set. If it isn't, then this is a programming error: use &error_abort. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20231123143813.42632-3-philmd@linaro.org>
-rw-r--r--hw/arm/bcm2836.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 166dc896c0..a1bd1406e1 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -131,10 +131,8 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n;
/* set periphbase/CBAR value for CPU-local registers */
- if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
- bc->peri_base, errp)) {
- return;
- }
+ object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar",
+ bc->peri_base, &error_abort);
/* start powered off if not enabled */
if (!object_property_set_bool(OBJECT(&s->cpu[n].core),