diff options
| author | Cédric Le Goater <clg@kaod.org> | 2020-01-27 15:41:52 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2020-02-02 14:07:57 +1100 |
| commit | a9ec49af3b2a5a83004d1766bf7a4b4f63f7c8a6 (patch) | |
| tree | eedbbe819729b5c179d9de3ce2e800898cb7cdf2 | |
| parent | 12b3868eadf0d5c5ada24f7036c55de7943575a9 (diff) | |
ppc/pnv: Add support for HRMOR on Radix host
When in HV mode, if EA[0] is 0, the Hypervisor Offset Real Mode
Register controls the access.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144154.10170-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target/ppc/mmu-radix64.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 066e324464..224e646c50 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -235,6 +235,12 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, /* In real mode top 4 effective addr bits (mostly) ignored */ raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; + /* In HV mode, add HRMOR if top EA bit is clear */ + if (msr_hv || !env->has_hv_mode) { + if (!(eaddr >> 63)) { + raddr |= env->spr[SPR_HRMOR]; + } + } tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); |