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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-03 11:34:25 -0500 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-10-05 12:57:41 -0500 |
| commit | 739df333dc8853ae6578492675a26a601d6be077 (patch) | |
| tree | 641df18e332baf52de05065f5de02677350dad84 | |
| parent | b299e88d4261b0af30190e74005ad930e04f3a11 (diff) | |
softfloat: Specialize udiv_qrnnd for s390x
The ISA has a 128/64-bit division instruction.
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | include/fpu/softfloat-macros.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index 39eb08b4f1..eafc68932b 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -641,6 +641,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, uint64_t q; asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); return q; +#elif defined(__s390x__) + /* Need to use a TImode type to get an even register pair for DLGR. */ + unsigned __int128 n = (unsigned __int128)n1 << 64 | n0; + asm("dlgr %0, %1" : "+r"(n) : "r"(d)); + *r = n >> 64; + return n; #else uint64_t d0, d1, q0, q1, r1, r0, m; |