diff options
| author | Song Gao <gaosong@loongson.cn> | 2023-05-04 20:27:58 +0800 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-05-06 11:19:48 +0800 |
| commit | ac95a0b975583de1ea70e03b70b8c866c109324c (patch) | |
| tree | 5e8def4160d9264d249b8a90df4ae9d2d011ae7c | |
| parent | 0b1e67051d5853eaca5336c50115b8f6c9289e96 (diff) | |
target/loongarch: Implement vfrstp
This patch includes:
- VFRSTP[I].{B/H}.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-33-gaosong@loongson.cn>
| -rw-r--r-- | target/loongarch/disas.c | 5 | ||||
| -rw-r--r-- | target/loongarch/helper.h | 5 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_lsx.c.inc | 5 | ||||
| -rw-r--r-- | target/loongarch/insns.decode | 5 | ||||
| -rw-r--r-- | target/loongarch/lsx_helper.c | 41 |
5 files changed, 61 insertions, 0 deletions
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 48c7ea47a4..be2bb9cc42 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1297,3 +1297,8 @@ INSN_LSX(vbitrevi_b, vv_i) INSN_LSX(vbitrevi_h, vv_i) INSN_LSX(vbitrevi_w, vv_i) INSN_LSX(vbitrevi_d, vv_i) + +INSN_LSX(vfrstp_b, vvv) +INSN_LSX(vfrstp_h, vvv) +INSN_LSX(vfrstpi_b, vv_i) +INSN_LSX(vfrstpi_h, vv_i) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 75120ca55e..2cc235d019 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -512,3 +512,8 @@ DEF_HELPER_FLAGS_4(vbitrevi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vbitrevi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vbitrevi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(vbitrevi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + +DEF_HELPER_4(vfrstp_b, void, env, i32, i32, i32) +DEF_HELPER_4(vfrstp_h, void, env, i32, i32, i32) +DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32) +DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 86243b54ba..ee84a5a4ee 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -3416,3 +3416,8 @@ TRANS(vbitrevi_b, gvec_vv_i, MO_8, do_vbitrevi) TRANS(vbitrevi_h, gvec_vv_i, MO_16, do_vbitrevi) TRANS(vbitrevi_w, gvec_vv_i, MO_32, do_vbitrevi) TRANS(vbitrevi_d, gvec_vv_i, MO_64, do_vbitrevi) + +TRANS(vfrstp_b, gen_vvv, gen_helper_vfrstp_b) +TRANS(vfrstp_h, gen_vvv, gen_helper_vfrstp_h) +TRANS(vfrstpi_b, gen_vv_i, gen_helper_vfrstpi_b) +TRANS(vfrstpi_h, gen_vv_i, gen_helper_vfrstpi_h) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 801c97714e..4cb286ffe5 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -998,3 +998,8 @@ vbitrevi_b 0111 00110001 10000 01 ... ..... ..... @vv_ui3 vbitrevi_h 0111 00110001 10000 1 .... ..... ..... @vv_ui4 vbitrevi_w 0111 00110001 10001 ..... ..... ..... @vv_ui5 vbitrevi_d 0111 00110001 1001 ...... ..... ..... @vv_ui6 + +vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv +vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv +vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5 +vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5 diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c index 14e2df254d..66e9d405a4 100644 --- a/target/loongarch/lsx_helper.c +++ b/target/loongarch/lsx_helper.c @@ -2019,3 +2019,44 @@ DO_BITI(vbitrevi_b, 8, UB, DO_BITREV) DO_BITI(vbitrevi_h, 16, UH, DO_BITREV) DO_BITI(vbitrevi_w, 32, UW, DO_BITREV) DO_BITI(vbitrevi_d, 64, UD, DO_BITREV) + +#define VFRSTP(NAME, BIT, MASK, E) \ +void HELPER(NAME)(CPULoongArchState *env, \ + uint32_t vd, uint32_t vj, uint32_t vk) \ +{ \ + int i, m; \ + VReg *Vd = &(env->fpr[vd].vreg); \ + VReg *Vj = &(env->fpr[vj].vreg); \ + VReg *Vk = &(env->fpr[vk].vreg); \ + \ + for (i = 0; i < LSX_LEN/BIT; i++) { \ + if (Vj->E(i) < 0) { \ + break; \ + } \ + } \ + m = Vk->E(0) & MASK; \ + Vd->E(m) = i; \ +} + +VFRSTP(vfrstp_b, 8, 0xf, B) +VFRSTP(vfrstp_h, 16, 0x7, H) + +#define VFRSTPI(NAME, BIT, E) \ +void HELPER(NAME)(CPULoongArchState *env, \ + uint32_t vd, uint32_t vj, uint32_t imm) \ +{ \ + int i, m; \ + VReg *Vd = &(env->fpr[vd].vreg); \ + VReg *Vj = &(env->fpr[vj].vreg); \ + \ + for (i = 0; i < LSX_LEN/BIT; i++) { \ + if (Vj->E(i) < 0) { \ + break; \ + } \ + } \ + m = imm % (LSX_LEN/BIT); \ + Vd->E(m) = i; \ +} + +VFRSTPI(vfrstpi_b, 8, B) +VFRSTPI(vfrstpi_h, 16, H) |