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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-28 18:16:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-03-30 11:16:17 -0700 |
| commit | e20cb81d9c5a3d0f9c08f3642728a210a1c162c9 (patch) | |
| tree | 74f5c4a2067fb61b376894b3c93eeb7f0d8ae802 | |
| parent | 84878f4c00a7beca1d1460e2f77a6c833b8d0393 (diff) | |
tcg/i386: Fix INDEX_op_dup2_vec
We were only constructing the 64-bit element, and not
replicating the 64-bit element across the rest of the vector.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/i386/tcg-target.inc.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 223dba9c8c..7f61eeedd0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2855,9 +2855,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, goto gen_simd; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_dup2_vec: - /* Constraints have already placed both 32-bit inputs in xmm regs. */ - insn = OPC_PUNPCKLDQ; - goto gen_simd; + /* First merge the two 32-bit inputs to a single 64-bit element. */ + tcg_out_vex_modrm(s, OPC_PUNPCKLDQ, a0, a1, a2); + /* Then replicate the 64-bit elements across the rest of the vector. */ + if (type != TCG_TYPE_V64) { + tcg_out_dup_vec(s, type, MO_64, a0, a0); + } + break; #endif case INDEX_op_abs_vec: insn = abs_insn[vece]; |