diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-12-07 09:28:11 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-12-07 09:28:11 -0800 |
| commit | a216e7cf119c91ffdf5931834a1a030ebea40d70 (patch) | |
| tree | 60d00f01921722d1fdac86e1cbbe7095229c255d | |
| parent | 92ac58e34c008562a2a70b467b2a5efef5a1fe25 (diff) | |
| parent | 2958e5150dfa297dd5a51fe57a29156b8744f07f (diff) | |
Merge tag 'pull-target-arm-20211207' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
of maintenance interrupts
# gpg: Signature made Tue 07 Dec 2021 09:18:50 AM PST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20211207' of https://git.linaro.org/people/pmaydell/qemu-arm:
gicv3: fix ICH_MISR's LRENP computation
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fba931450..85fc369e55 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) /* Scan list registers and fill in the U, NP and EOI bits */ eoi_maintenance_interrupt_state(cs, &value); - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { value |= ICH_MISR_EL2_LRENP; } |