diff options
| author | Emilio G. Cota <cota@braap.org> | 2018-03-05 17:13:30 -0500 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2018-05-20 08:25:23 +0300 |
| commit | 1d349821551c2da4dfefe36c6ac17319f33ebbd5 (patch) | |
| tree | fc5557b4604e8bab2bbf178345a1867c024fc9bc | |
| parent | 5bcf917ee37a5efbef99f091a96db54a5276becb (diff) | |
tcg: fix s/compliment/complement/ typos
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | target/i386/translate.c | 2 | ||||
| -rw-r--r-- | target/m68k/translate.c | 2 | ||||
| -rw-r--r-- | tcg/README | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/target/i386/translate.c b/target/i386/translate.c index b0f69838f2..7c21814676 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -113,7 +113,7 @@ typedef struct DisasContext { int rex_x, rex_b; #endif int vex_l; /* vex vector length */ - int vex_v; /* vex vvvv register, without 1's compliment. */ + int vex_v; /* vex vvvv register, without 1's complement. */ int ss32; /* 32 bit stack segment */ CCOp cc_op; /* current CC operation */ bool cc_op_dirty; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 44a0ac4e2e..8959e4d0f0 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4002,7 +4002,7 @@ DISAS_INSN(bfext_reg) TCGv shift; /* In general, we're going to rotate the field so that it's at the - top of the word and then right-shift by the compliment of the + top of the word and then right-shift by the complement of the width to extend the field. */ if (ext & 0x20) { /* Variable width. */ diff --git a/tcg/README b/tcg/README index a5237a9edb..d22ee084b8 100644 --- a/tcg/README +++ b/tcg/README @@ -561,7 +561,7 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. * orc_vec v0, v1, v2 * not_vec v0, v1 - Similarly, logical operations with and without compliment. + Similarly, logical operations with and without complement. Note that VECE is unused. * shli_vec v0, v1, i2 |