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authorPeter Maydell <peter.maydell@linaro.org>2021-04-30 14:27:39 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-05-10 13:24:09 +0100
commitb5c8a457fab78e08d0ab5f9ca242b85b31c72c87 (patch)
treed8f991d33b37b0a2d3b9c8b2bc3cde32b62515e7
parent9194a9cbc75e7af63eff26c87b995bdc52078ca6 (diff)
target/arm: Make functions used by translate-neon global
Make the remaining functions needed by the translate-neon code global. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210430132740.10391-13-peter.maydell@linaro.org
-rw-r--r--target/arm/translate-a32.h8
-rw-r--r--target/arm/translate.c10
2 files changed, 10 insertions, 8 deletions
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h
index e767366f69..3ddb76b76b 100644
--- a/target/arm/translate-a32.h
+++ b/target/arm/translate-a32.h
@@ -39,6 +39,8 @@ void gen_set_pc_im(DisasContext *s, target_ulong val);
void gen_lookup_tb(DisasContext *s);
long vfp_reg_offset(bool dp, unsigned reg);
long neon_full_reg_offset(unsigned reg);
+long neon_element_offset(int reg, int element, MemOp memop);
+void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
static inline TCGv_i32 load_cpu_offset(int offset)
{
@@ -130,4 +132,10 @@ DO_GEN_ST(32, MO_UL)
/* Set NZCV flags from the high 4 bits of var. */
#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
+/* Swap low and high halfwords. */
+static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
+{
+ tcg_gen_rotri_i32(dest, var, 16);
+}
+
#endif
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7ff0425c75..18de16ebd0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -325,7 +325,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
}
/* Byteswap each halfword. */
-static void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
+void gen_rev16(TCGv_i32 dest, TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
@@ -346,12 +346,6 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
tcg_gen_ext16s_i32(dest, var);
}
-/* Swap low and high halfwords. */
-static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
-{
- tcg_gen_rotri_i32(dest, var, 16);
-}
-
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
tmp = (t0 ^ t1) & 0x8000;
t0 &= ~0x8000;
@@ -1104,7 +1098,7 @@ long neon_full_reg_offset(unsigned reg)
* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
* where 0 is the least significant end of the register.
*/
-static long neon_element_offset(int reg, int element, MemOp memop)
+long neon_element_offset(int reg, int element, MemOp memop)
{
int element_size = 1 << (memop & MO_SIZE);
int ofs = element * element_size;