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authorAurelien Jarno <aurelien@aurel32.net>2010-04-09 20:52:48 +0200
committerAurelien Jarno <aurelien@aurel32.net>2010-04-19 07:03:06 +0200
commit914ccf51b07af860021863e0f8e46eac9ffbcb68 (patch)
treea879811d8bc42a82063741d8c1817347bd6d559a
parentbf5675efe33888fe058210be98259a34faf4d4e5 (diff)
tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--tcg/arm/tcg-target.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index a60637e54d..c07d28415e 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -89,10 +89,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#endif
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
- TCG_REG_R2,
- TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
TCG_REG_R6,
@@ -101,8 +97,12 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
- TCG_REG_R12,
TCG_REG_R13,
+ TCG_REG_R0,
+ TCG_REG_R1,
+ TCG_REG_R2,
+ TCG_REG_R3,
+ TCG_REG_R12,
TCG_REG_R14,
};