diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-09-16 21:05:03 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | a6779861fd7d5dc8f90e89bd1fae3e689f9b8f65 (patch) | |
| tree | 9df25afca8e1fcc2f90674cb986d6caa9b9add98 | |
| parent | e12c63090be5b5eda50a9f30c8292c17823c6fb0 (diff) | |
target/hppa: Remove get_temp_tl
Replace with tcg_temp_new_tl without recording into ctx.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/hppa/translate.c | 28 |
1 files changed, 3 insertions, 25 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 99b9fc0561..3c4a759628 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -254,9 +254,6 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; - int ntempl; - TCGv_tl templ[4]; - DisasCond null_cond; TCGLabel *null_lab; @@ -491,15 +488,6 @@ static void cond_free(DisasCond *cond) } } -#ifndef CONFIG_USER_ONLY -static TCGv_tl get_temp_tl(DisasContext *ctx) -{ - unsigned i = ctx->ntempl++; - g_assert(i < ARRAY_SIZE(ctx->templ)); - return ctx->templ[i] = tcg_temp_new_tl(); -} -#endif - static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t = tcg_temp_new(); @@ -1374,7 +1362,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) if (sp < 0) { sp = ~sp; } - spc = get_temp_tl(ctx); + spc = tcg_temp_new_tl(); load_spr(ctx, spc, sp); return spc; } @@ -1384,7 +1372,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) ptr = tcg_temp_new_ptr(); tmp = tcg_temp_new(); - spc = get_temp_tl(ctx); + spc = tcg_temp_new_tl(); tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); tcg_gen_andi_reg(tmp, tmp, 030); @@ -1420,7 +1408,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, #ifdef CONFIG_USER_ONLY *pgva = (modify <= 0 ? ofs : base); #else - TCGv_tl addr = get_temp_tl(ctx); + TCGv_tl addr = tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); @@ -4081,9 +4069,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) /* Bound the number of instructions by those left on the page. */ bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns = MIN(ctx->base.max_insns, bound); - - ctx->ntempl = 0; - memset(ctx->templ, 0, sizeof(ctx->templ)); } static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) @@ -4112,7 +4097,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); CPUHPPAState *env = cpu_env(cs); DisasJumpType ret; - int i, n; /* Execute one insn. */ #ifdef CONFIG_USER_ONLY @@ -4151,12 +4135,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } } - /* Forget any temporaries allocated. */ - for (i = 0, n = ctx->ntempl; i < n; ++i) { - ctx->templ[i] = NULL; - } - ctx->ntempl = 0; - /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) { |