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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-03 13:31:30 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-03 13:31:30 +0000
commit8e27dd6f09df9ca028edffae5df5b562d9d40cae (patch)
tree2043ffcd96b1c9c79c525bcf9899d873df20b043
parentd6a46fe8c264b5853ccf8f966f7bd00c1c32c877 (diff)
Add GEN_VXFORM macro for subsequent instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6154 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-ppc/translate.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c64f936af0..d89f09c24d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6164,6 +6164,23 @@ GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
+#define GEN_VXFORM(name, opc2, opc3) \
+GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
+{ \
+ TCGv_ptr ra, rb, rd; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ ra = gen_avr_ptr(rA(ctx->opcode)); \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ rd = gen_avr_ptr(rD(ctx->opcode)); \
+ gen_helper_##name (rd, ra, rb); \
+ tcg_temp_free_ptr(ra); \
+ tcg_temp_free_ptr(rb); \
+ tcg_temp_free_ptr(rd); \
+}
+
/*** SPE extension ***/
/* Register moves */