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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-04 22:08:48 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-04 22:08:48 +0000
commit2c2779080c2dbdeaefca59742be9648dd1878044 (patch)
tree5c57c87969ec3876e873adcc1029612b20f1323b
parent3b43004804f01a07e65714e936af9a6cf0c62473 (diff)
Add vmul{e,o}{s,u}{b,h} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-ppc/helper.h8
-rw-r--r--target-ppc/op_helper.c22
-rw-r--r--target-ppc/translate.c8
3 files changed, 38 insertions, 0 deletions
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ca17cf7a6f..3b44b97803 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -129,6 +129,14 @@ DEF_HELPER_3(vmrglw, void, avr, avr, avr)
DEF_HELPER_3(vmrghb, void, avr, avr, avr)
DEF_HELPER_3(vmrghh, void, avr, avr, avr)
DEF_HELPER_3(vmrghw, void, avr, avr, avr)
+DEF_HELPER_3(vmulesb, void, avr, avr, avr)
+DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleub, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosb, void, avr, avr, avr)
+DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmuloub, void, avr, avr, avr)
+DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_1(efscfsi, i32, i32)
DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3e495a1b12..4a548ea136 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2066,6 +2066,28 @@ VMRG(w, u32)
#undef MRGHI
#undef MRGLO
+#define VMUL_DO(name, mul_element, prod_element, evenp) \
+ void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ { \
+ int i; \
+ VECTOR_FOR_INORDER_I(i, prod_element) { \
+ if (evenp) { \
+ r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
+ } else { \
+ r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
+ } \
+ } \
+ }
+#define VMUL(suffix, mul_element, prod_element) \
+ VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
+ VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
+VMUL(sb, s8, s16)
+VMUL(sh, s16, s32)
+VMUL(ub, u8, u16)
+VMUL(uh, u16, u32)
+#undef VMUL_DO
+#undef VMUL
+
#undef VECTOR_FOR_INORDER_I
#undef HI_IDX
#undef LO_IDX
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bc84fca7a9..eed3999105 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6211,6 +6211,14 @@ GEN_VXFORM(vmrghw, 6, 2);
GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
+GEN_VXFORM(vmuloub, 4, 0);
+GEN_VXFORM(vmulouh, 4, 1);
+GEN_VXFORM(vmulosb, 4, 4);
+GEN_VXFORM(vmulosh, 4, 5);
+GEN_VXFORM(vmuleub, 4, 8);
+GEN_VXFORM(vmuleuh, 4, 9);
+GEN_VXFORM(vmulesb, 4, 12);
+GEN_VXFORM(vmulesh, 4, 13);
/*** SPE extension ***/
/* Register moves */