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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-07 22:38:16 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2015-05-22 17:02:34 +0200 |
| commit | 9e14a7b24f4cff93da664fdcfecad41fbd229e2b (patch) | |
| tree | 2129a22707c8d8603c7a591d883eb5f990ef320a | |
| parent | bc3551c43308dd77bc1cc9a4e39962b2afd4dffc (diff) | |
target-tricore: add FCALL instructions of the v1.6 ISA
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-tricore/translate.c | 26 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 3 |
2 files changed, 29 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 4aea0c632a..76bab8e5de 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3275,6 +3275,18 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset) gen_goto_tb(ctx, 0, ctx->next_pc); } +static void gen_fcall_save_ctx(DisasContext *ctx) +{ + TCGv temp = tcg_temp_new(); + + tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); + tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); + tcg_gen_mov_tl(cpu_gpr_a[10], temp); + + tcg_temp_free(temp); +} + static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { @@ -3369,6 +3381,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_helper_1arg(call, ctx->next_pc); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; + case OPC1_32_B_FCALL: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + break; + case OPC1_32_B_FCALLA: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); + break; case OPC1_32_B_JLA: tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); /* fall through */ @@ -6311,6 +6331,10 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) gen_helper_1arg(call, ctx->next_pc); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; + case OPC2_32_RR_FCALLI: + gen_fcall_save_ctx(ctx); + tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); + break; } tcg_gen_exit_tb(0); ctx->bstate = BS_BRANCH; @@ -7946,6 +7970,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) /* B-format */ case OPC1_32_B_CALL: case OPC1_32_B_CALLA: + case OPC1_32_B_FCALL: + case OPC1_32_B_FCALLA: case OPC1_32_B_J: case OPC1_32_B_JA: case OPC1_32_B_JL: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index d1506a9429..bb1939cb65 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -428,6 +428,8 @@ enum { /* B Format */ OPC1_32_B_CALL = 0x6d, OPC1_32_B_CALLA = 0xed, + OPC1_32_B_FCALL = 0x61, + OPC1_32_B_FCALLA = 0xe1, OPC1_32_B_J = 0x1d, OPC1_32_B_JA = 0x9d, OPC1_32_B_JL = 0x5d, @@ -1127,6 +1129,7 @@ enum { OPC2_32_RR_JI = 0x03, OPC2_32_RR_JLI = 0x02, OPC2_32_RR_CALLI = 0x00, + OPC2_32_RR_FCALLI = 0x01, }; /* * RR1 Format |