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authorRichard Henderson <rth@twiddle.net>2013-01-23 18:12:13 -0800
committerRichard Henderson <rth@twiddle.net>2013-02-18 15:52:32 -0800
commit4a554890e479a43568de8b5354d9ca8583f5ec7f (patch)
tree2bc37dd81853479ac118cbc080ef1597d48f8286
parent0592f74a75ab695efd48a151219667adc0fa7cc4 (diff)
target-i386: Implement SHLX, SARX, SHRX
Signed-off-by: Richard Henderson <rth@twiddle.net>
-rw-r--r--target-i386/translate.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 51016fedd5..c1a2886acc 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4174,6 +4174,37 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]);
break;
+ case 0x1f7: /* shlx Gy, Ey, By */
+ case 0x2f7: /* sarx Gy, Ey, By */
+ case 0x3f7: /* shrx Gy, Ey, By */
+ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
+ || !(s->prefix & PREFIX_VEX)
+ || s->vex_l != 0) {
+ goto illegal_op;
+ }
+ ot = (s->dflag == 2 ? OT_QUAD : OT_LONG);
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+ if (ot == OT_QUAD) {
+ tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 63);
+ } else {
+ tcg_gen_andi_tl(cpu_T[1], cpu_regs[s->vex_v], 31);
+ }
+ if (b == 0x1f7) {
+ tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ } else if (b == 0x2f7) {
+ if (ot != OT_QUAD) {
+ tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
+ }
+ tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ } else {
+ if (ot != OT_QUAD) {
+ tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
+ }
+ tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ }
+ gen_op_mov_reg_T0(ot, reg);
+ break;
+
case 0x0f3:
case 0x1f3:
case 0x2f3: