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| author | Max Filippov <jcmvbkbc@gmail.com> | 2012-05-27 18:34:50 +0400 |
|---|---|---|
| committer | Michael Roth <mdroth@linux.vnet.ibm.com> | 2012-06-25 08:48:06 -0500 |
| commit | b696aeab6ad6abe3b45fac96264a40a555ff64ce (patch) | |
| tree | 415ca8e88c3eca7cc7e0a2444094f77b14eb2d78 | |
| parent | 6514fe50471ca277c461435b17771e91c115b010 (diff) | |
target-xtensa: update EXCVADDR in case of page table lookup
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, even
if the miss is handled entirely by processor hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
(cherry picked from commit 39e7d37f0f25823c00d1105e8eb9b61182fd349c)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| -rw-r--r-- | target-xtensa/helper.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 2094227843..43a6611e62 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -516,6 +516,7 @@ static int autorefill_mmu(CPUXtensaState *env, uint32_t vaddr, bool dtlb, *wi = (++env->autorefill_idx) & 0x3; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, *wi, ei); xtensa_tlb_set_entry(env, dtlb, *wi, *ei, vpn, pte); + env->sregs[EXCVADDR] = vaddr; qemu_log("%s: autorefill(%08x): %08x -> %08x\n", __func__, vaddr, vpn, pte); } |