Hexagon (target/hexagon) Add overrides for count trailing zeros/ones

The following instructions are overriden
    S2_ct0            Count trailing zeros
    S2_ct1            Count trailing ones
    S2_ct0p           Count trailing zeros (register pair)
    S2_ct1p           Count trailing ones (register pair)

These instructions are not handled by idef-parser because the
imported semantics uses bit-reverse.  However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230405164211.30015-1-tsimpson@quicinc.com>

2 files changed, 79 insertions, 1 deletions

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index bcf0cf466a..45f92adf6c 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1058,6 +1058,30 @@
 #define fGEN_TCG_SL2_jumpr31_fnew(SHORTCODE) \
     gen_cond_jumpr31(ctx, TCG_COND_NE, hex_new_pred_value[0])
 
+/* Count trailing zeros/ones */
+#define fGEN_TCG_S2_ct0(SHORTCODE) \
+    do { \
+        tcg_gen_ctzi_tl(RdV, RsV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct1(SHORTCODE) \
+    do { \
+        tcg_gen_not_tl(RdV, RsV); \
+        tcg_gen_ctzi_tl(RdV, RdV, 32); \
+    } while (0)
+#define fGEN_TCG_S2_ct0p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_ctzi_i64(tmp, RssV, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+#define fGEN_TCG_S2_ct1p(SHORTCODE) \
+    do { \
+        TCGv_i64 tmp = tcg_temp_new_i64(); \
+        tcg_gen_not_i64(tmp, RssV); \
+        tcg_gen_ctzi_i64(tmp, tmp, 64); \
+        tcg_gen_extrl_i64_i32(RdV, tmp); \
+    } while (0)
+
 /* Floating point */
 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
     gen_helper_conv_sf2df(RddV, cpu_env, RsV)
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index e73ab57334..e126751e3a 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
 typedef unsigned char uint8_t;
 typedef unsigned short uint16_t;
 typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
 
 
 static inline void S4_storerhnew_rr(void *p, int index, uint16_t v)
@@ -333,6 +334,57 @@ void test_l2fetch(void)
                   "l2fetch(r0, r3:2)\n\t");
 }
 
+static inline int ct0(uint32_t x)
+{
+    int res;
+    asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct1(uint32_t x)
+{
+    int res;
+    asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct0p(uint64_t x)
+{
+    int res;
+    asm("%0 = ct0(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+static inline int ct1p(uint64_t x)
+{
+    int res;
+    asm("%0 = ct1(%1)\n\t" : "=r"(res) : "r"(x));
+    return res;
+}
+
+void test_count_trailing_zeros_ones(void)
+{
+    check(ct0(0x0000000f), 0);
+    check(ct0(0x00000000), 32);
+    check(ct0(0x000000f0), 4);
+
+    check(ct1(0x000000f0), 0);
+    check(ct1(0x0000000f), 4);
+    check(ct1(0x00000000), 0);
+    check(ct1(0xffffffff), 32);
+
+    check(ct0p(0x000000000000000fULL), 0);
+    check(ct0p(0x0000000000000000ULL), 64);
+    check(ct0p(0x00000000000000f0ULL), 4);
+
+    check(ct1p(0x00000000000000f0ULL), 0);
+    check(ct1p(0x000000000000000fULL), 4);
+    check(ct1p(0x0000000000000000ULL), 0);
+    check(ct1p(0xffffffffffffffffULL), 64);
+    check(ct1p(0xffffffffff0fffffULL), 20);
+    check(ct1p(0xffffff0fffffffffULL), 36);
+}
+
 int main()
 {
     int res;
@@ -468,6 +520,8 @@ int main()
 
     test_l2fetch();
 
+    test_count_trailing_zeros_ones();
+
     puts(err ? "FAIL" : "PASS");
     return err;
 }