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authorRichard Henderson <richard.henderson@linaro.org>2023-06-02 01:33:15 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-07-09 13:47:11 +0100
commit7a70583a4109a177468beab378177b2285344b7a (patch)
tree0bcaf254fa38b27c6ae130ad30505b12e4982dfe
parentcad26538e8579bb7f4bc6374e4b4155151bc2598 (diff)
target/riscv: Use aesdec_ISB_ISR_AK
This implements the AES64DS instruction. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--target/riscv/crypto_helper.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index b072fed3e2..e61f7fe1e5 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -213,7 +213,12 @@ target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
{
- return aes64_operation(rs1, rs2, false, false);
+ AESState t;
+
+ t.d[HOST_BIG_ENDIAN] = rs1;
+ t.d[!HOST_BIG_ENDIAN] = rs2;
+ aesdec_ISB_ISR_AK(&t, &t, &aes_zero, false);
+ return t.d[HOST_BIG_ENDIAN];
}
target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)