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authorKwok Cheung Yeung <kcy@codesourcery.com>2013-05-17 14:51:21 -0700
committerAurelien Jarno <aurelien@aurel32.net>2013-05-20 18:16:17 +0200
commit1239b472bb0dba8060f1af29d40dafbc1b2860d4 (patch)
tree6e2d54f5a06b03a0d274af56cbda5ccb180eeb96
parentea3164aafccdfdd8a9543787cdfa25fac30a5def (diff)
linux-user: Save the correct resume address for MIPS signal handling
The current ISA mode needs to be saved in bit 0 of the resume address. If the current instruction happens to be in a branch delay slot, then the address of the preceding jump instruction should be stored instead. exception_resume_pc already does both of these tasks, so it is made available and reused. MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the first instruction of the signal handler as a delay slot instruction. Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--linux-user/signal.c3
-rw-r--r--target-mips/cpu.h1
-rw-r--r--target-mips/helper.c4
3 files changed, 5 insertions, 3 deletions
diff --git a/linux-user/signal.c b/linux-user/signal.c
index dc34ae7bbb..5da8452b2a 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -2528,7 +2528,8 @@ setup_sigcontext(CPUMIPSState *regs, struct target_sigcontext *sc)
int err = 0;
int i;
- err |= __put_user(regs->active_tc.PC, &sc->sc_pc);
+ err |= __put_user(exception_resume_pc(regs), &sc->sc_pc);
+ regs->hflags &= ~MIPS_HFLAG_BMASK;
__put_user(0, &sc->sc_regs[0]);
for (i = 1; i < 32; ++i) {
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index cedf03df43..6e761e03b6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw);
#endif
+target_ulong exception_resume_pc (CPUMIPSState *env);
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 3a54acf706..36929ddee7 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_CACHE] = "cache error",
};
-#if !defined(CONFIG_USER_ONLY)
-static target_ulong exception_resume_pc (CPUMIPSState *env)
+target_ulong exception_resume_pc (CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env)
return bad_pc;
}
+#if !defined(CONFIG_USER_ONLY)
static void set_hflags_for_handler (CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */