diff options
| author | Artyom Tarasenko <atar4qemu@gmail.com> | 2016-11-02 10:37:44 +0100 |
|---|---|---|
| committer | Artyom Tarasenko <atar4qemu@gmail.com> | 2017-01-18 22:03:44 +0100 |
| commit | 3390537b5df4014e24a30f9bdcfa05c2bd0cd6d8 (patch) | |
| tree | 980266b3bcd1df564a797415a1e7ccf5f5b4be56 | |
| parent | 7285fba083de3f14f6e98abb4469173b56da9480 (diff) | |
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.
"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"
Integer stores of all sizes are allowed with these ASIs.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
| -rw-r--r-- | target/sparc/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0f20ed0511..655060cd9a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2321,8 +2321,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, case GET_ASI_EXCP: break; case GET_ASI_DTWINX: /* Reserved for stda. */ +#ifndef TARGET_SPARC64 gen_exception(dc, TT_ILL_INSN); break; +#else + if (!(dc->def->features & CPU_FEATURE_HYPV)) { + /* Pre OpenSPARC CPUs don't have these */ + gen_exception(dc, TT_ILL_INSN); + return; + } + /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions + * are ST_BLKINIT_ ASIs */ + /* fall through */ +#endif case GET_ASI_DIRECT: gen_address_mask(dc, addr); tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); |