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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-06-26 08:35:18 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-06-26 08:35:18 +0000
commit88fe8a41f2abbee28948626a4e6426d17f0498bf (patch)
treea0cc7663595696979a4203af8153df8f6b694761
parentb3ceef24f4fee8d5ed96b8c4a5d3e80c0a651f0b (diff)
DR6 single step exception status bit, by Juergen Keil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3024 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-i386/exec.h1
-rw-r--r--target-i386/helper.c6
-rw-r--r--target-i386/op.c5
-rw-r--r--target-i386/translate.c2
4 files changed, 13 insertions, 1 deletions
diff --git a/target-i386/exec.h b/target-i386/exec.h
index f6d05e0358..f48462aaa1 100644
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -190,6 +190,7 @@ void helper_divq_EAX_T0(void);
void helper_idivq_EAX_T0(void);
void helper_bswapq_T0(void);
void helper_cmpxchg8b(void);
+void helper_single_step(void);
void helper_cpuid(void);
void helper_enter_level(int level, int data32);
void helper_enter64_level(int level, int data64);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 951fdc5732..3c051b9ea3 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1622,6 +1622,12 @@ void helper_cmpxchg8b(void)
CC_SRC = eflags;
}
+void helper_single_step()
+{
+ env->dr[6] |= 0x4000;
+ raise_exception(EXCP01_SSTP);
+}
+
void helper_cpuid(void)
{
uint32_t index;
diff --git a/target-i386/op.c b/target-i386/op.c
index a8cfce271b..ea8aec6b51 100644
--- a/target-i386/op.c
+++ b/target-i386/op.c
@@ -730,6 +730,11 @@ void OPPROTO op_cmpxchg8b(void)
helper_cmpxchg8b();
}
+void OPPROTO op_single_step(void)
+{
+ helper_single_step();
+}
+
void OPPROTO op_movl_T0_0(void)
{
T0 = 0;
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 393db0d65e..15bfef5cbf 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2277,7 +2277,7 @@ static void gen_eob(DisasContext *s)
if (s->singlestep_enabled) {
gen_op_debug();
} else if (s->tf) {
- gen_op_raise_exception(EXCP01_SSTP);
+ gen_op_single_step();
} else {
gen_op_movl_T0_0();
gen_op_exit_tb();