diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-21 19:28:48 -0700 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-25 10:56:28 -0700 |
commit | 73bc0bd41b84aaee489118da1d20901d27f3654a (patch) | |
tree | 3514eac3ef5f15237d085569e6023f6470c28c3f | |
parent | 707526ad865dc4064c3984bcc061596a21bf9d3b (diff) |
cputlb: Handle TLB_NOTDIRTY in probe_access
We can use notdirty_write for the write and return a valid host
pointer for this case.
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r-- | accel/tcg/cputlb.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3e91838519..b56e9ddf8c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1168,16 +1168,24 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return NULL; } - /* Handle watchpoints. */ - if (tlb_addr & TLB_WATCHPOINT) { - cpu_check_watchpoint(env_cpu(env), addr, size, - env_tlb(env)->d[mmu_idx].iotlb[index].attrs, - wp_access, retaddr); - } + if (unlikely(tlb_addr & TLB_FLAGS_MASK)) { + CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; - /* Reject I/O access, or other required slow-path. */ - if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) { - return NULL; + /* Reject I/O access, or other required slow-path. */ + if (tlb_addr & (TLB_MMIO | TLB_BSWAP | TLB_DISCARD_WRITE)) { + return NULL; + } + + /* Handle watchpoints. */ + if (tlb_addr & TLB_WATCHPOINT) { + cpu_check_watchpoint(env_cpu(env), addr, size, + iotlbentry->attrs, wp_access, retaddr); + } + + /* Handle clean RAM pages. */ + if (tlb_addr & TLB_NOTDIRTY) { + notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); + } } return (void *)((uintptr_t)addr + entry->addend); |