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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-04 13:17:17 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-04 13:17:17 +0000
commit0c5f3c8d7d77307d79c6f764ef62ce6ffb3bc9e8 (patch)
treeddfdf9a511f31ec8a48cc125ee15798e992bcc97
parent9027db892a56577f2e421091848ef97e59261030 (diff)
Mention output overlaps.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5619 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--tcg/README5
1 files changed, 5 insertions, 0 deletions
diff --git a/tcg/README b/tcg/README
index 7e7c06b41c..bdb44dfd3b 100644
--- a/tcg/README
+++ b/tcg/README
@@ -390,6 +390,11 @@ GCC like constraints are used to define the constraints of every
instruction. Memory constraints are not supported in this
version. Aliases are specified in the input operands as for GCC.
+The same register may be used for both an input and an output, even when
+they are not explicitly aliased. If an op expands to multiple target
+instructions then care must be taken to avoid clobbering input values.
+GCC style "early clobber" outputs are not currently supported.
+
A target can define specific register or constant constraints. If an
operation uses a constant input constraint which does not allow all
constants, it must also accept registers in order to have a fallback.