diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 19:33:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-01 11:46:21 +0100 |
| commit | 5f07817eb94542e39a419baafa3026b15e8d33f7 (patch) | |
| tree | b59088f855cdf121f4b6a3f7c17d9297563ae637 | |
| parent | fc8ae790311882afa3c7816df004daf978c40e9a (diff) | |
target/arm: Enable FP16 in '-cpu max'
Set the MVFR1 ID register FPHP and SIMDHP fields to indicate
that our "-cpu max" has v8.2-FP16.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-46-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/cpu.c | 3 | ||||
| -rw-r--r-- | target/arm/cpu64.c | 10 |
2 files changed, 6 insertions, 7 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b382fcd60..c179e0752d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2143,7 +2143,8 @@ static void arm_max_initfn(Object *obj) cpu->isar.id_isar6 = t; t = cpu->isar.mvfr1; - t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ + t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ cpu->isar.mvfr1 = t; t = cpu->isar.mvfr2; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index dd696183df..3c2b3d9599 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -704,12 +704,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ cpu->isar.id_dfr0 = u; - /* - * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, - * so do not set MVFR1.FPHP. Strictly speaking this is not legal, - * but it is also not legal to enable SVE without support for FP16, - * and enabling SVE in system mode is more useful in the short term. - */ + u = cpu->isar.mvfr1; + u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ + u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 = u; #ifdef CONFIG_USER_ONLY /* For usermode -cpu max we can use a larger and more efficient DCZ |