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authorPeter Maydell <peter.maydell@linaro.org>2015-08-03 11:44:07 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-08-03 11:44:07 +0100
commitbd80b5963f58c601f31d3186b89887bf8e182fb5 (patch)
treef03a875cfc066c406e88038484784fa7ce1f719a
parentff90f84e74d7c8641a493585ba9ea8d6e0d19855 (diff)
parentc99d69694af4ed15b33e3f7c2e3ef6972c14358d (diff)
Merge remote-tracking branch 'remotes/aurel/tags/pull-tcg-mips-s390-20150803' into staging
TCG MIPS and S390 fixes for 2.4. # gpg: Signature made Mon Aug 3 09:09:59 2015 BST using RSA key ID 1DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-tcg-mips-s390-20150803: tcg/mips: fix add2 tcg/s390x: Mask TCGMemOp appropriately for indexing tcg/mips: Mask TCGMemOp appropriately for indexing tcg/mips: fix TLB loading for BE host with 32-bit guests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--tcg/mips/tcg-target.c11
-rw-r--r--tcg/s390/tcg-target.c4
2 files changed, 10 insertions, 5 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 668029977c..e97980df0b 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -963,9 +963,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
}
/* Load the tlb comparator. */
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
if (TARGET_LONG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
tcg_out_opc_imm(s, OPC_LW, base, TCG_REG_A0, cmp_off + HI_OFF);
+ } else {
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off);
}
/* Mask the page bits, keeping the alignment bits to compare against.
@@ -1103,7 +1105,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, TCGMemOp opc)
{
- switch (opc) {
+ switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB:
tcg_out_opc_imm(s, OPC_LBU, datalo, base, 0);
break;
@@ -1193,7 +1195,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg base, TCGMemOp opc)
{
- switch (opc) {
+ switch (opc & (MO_SIZE | MO_BSWAP)) {
case MO_8:
tcg_out_opc_imm(s, OPC_SB, datalo, base, 0);
break;
@@ -1269,6 +1271,9 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
if (cbl) {
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
+ } else if (rl == al && rl == bl) {
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
+ tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
} else {
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 921991ebfa..aa718eca0c 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -1390,7 +1390,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
- switch (opc) {
+ switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB:
tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
break;
@@ -1449,7 +1449,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
TCGReg base, TCGReg index, int disp)
{
- switch (opc) {
+ switch (opc & (MO_SIZE | MO_BSWAP)) {
case MO_UB:
if (disp >= 0 && disp < 0x1000) {
tcg_out_insn(s, RX, STC, data, base, index, disp);