diff options
author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 23:17:40 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-05 23:17:40 +0000 |
commit | 3529b538ce91df31b7300ce2fbd838a2ca36e1fc (patch) | |
tree | 07aafa47ef8300bcc9ec10e557e9f9ceb8423143 | |
parent | 1579a72ec5957297786ba5928e60571f4ab2f844 (diff) |
Fix disabling of the Cause register for R2.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2612 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | hw/mips_timer.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/hw/mips_timer.c b/hw/mips_timer.c index 055ee5b892..9128cbff7d 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -22,14 +22,11 @@ uint32_t cpu_mips_get_count (CPUState *env) 100 * 1000 * 1000, ticks_per_sec); } -static void cpu_mips_update_count (CPUState *env, uint32_t count, - uint32_t compare) +void cpu_mips_store_count (CPUState *env, uint32_t count) { uint64_t now, next; uint32_t tmp; - - if (env->CP0_Cause & (1 << CP0Ca_DC)) - return; + uint32_t compare = env->CP0_Compare; tmp = count; if (count == compare) @@ -52,14 +49,18 @@ static void cpu_mips_update_count (CPUState *env, uint32_t count, qemu_mod_timer(env->timer, next); } -void cpu_mips_store_count (CPUState *env, uint32_t value) +static void cpu_mips_update_count (CPUState *env, uint32_t count) { - cpu_mips_update_count(env, value, env->CP0_Compare); + if (env->CP0_Cause & (1 << CP0Ca_DC)) + return; + + cpu_mips_store_count(env, count); } void cpu_mips_store_compare (CPUState *env, uint32_t value) { - cpu_mips_update_count(env, cpu_mips_get_count(env), value); + env->CP0_Compare = value; + cpu_mips_update_count(env, cpu_mips_get_count(env)); if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) env->CP0_Cause &= ~(1 << CP0Ca_TI); cpu_mips_irq_request(env, 7, 0); @@ -75,7 +76,7 @@ static void mips_timer_cb (void *opaque) fprintf(logfile, "%s\n", __func__); } #endif - cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); + cpu_mips_update_count(env, cpu_mips_get_count(env)); if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) env->CP0_Cause |= 1 << CP0Ca_TI; cpu_mips_irq_request(env, 7, 1); @@ -85,6 +86,5 @@ void cpu_mips_clock_init (CPUState *env) { env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); env->CP0_Compare = 0; - cpu_mips_update_count(env, 1, 0); + cpu_mips_update_count(env, 1); } - |