aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorIsaku Yamahata <yamahata@valinux.co.jp>2009-11-12 14:58:47 +0900
committerMichael S. Tsirkin <mst@redhat.com>2009-12-01 17:52:47 +0200
commitd46636b88339ecc2cb8d10113f45ada164817773 (patch)
treeadda46d366348cb339668afede607a1022f4a4d5
parent10c9c329da60fe64ad24dba6f81044559ff15f9b (diff)
pci: pci bridge related clean up.
- fix bridge prefetchable memory accesser to check 64bit or not. - use pcibus_t consistently instead mixing pcibus_t and uint64_t. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-rw-r--r--hw/pci.c18
-rw-r--r--hw/pci.h1
2 files changed, 12 insertions, 7 deletions
diff --git a/hw/pci.c b/hw/pci.c
index bc566e5945..e26b3d0341 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -635,19 +635,23 @@ static uint32_t pci_config_get_io_base(PCIDevice *d,
return val;
}
-static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
+static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
{
- return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
+ return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
<< 16;
}
-static uint64_t pci_config_get_pref_base(PCIDevice *d,
+static pcibus_t pci_config_get_pref_base(PCIDevice *d,
uint32_t base, uint32_t upper)
{
- uint64_t val;
- val = ((uint64_t)pci_get_word(d->config + base) &
- PCI_PREF_RANGE_MASK) << 16;
- val |= (uint64_t)pci_get_long(d->config + upper) << 32;
+ pcibus_t tmp;
+ pcibus_t val;
+
+ tmp = (pcibus_t)pci_get_word(d->config + base);
+ val = (tmp & PCI_PREF_RANGE_MASK) << 16;
+ if (tmp & PCI_PREF_RANGE_TYPE_64) {
+ val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
+ }
return val;
}
diff --git a/hw/pci.h b/hw/pci.h
index 6a868f95de..0baf69bd5d 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -131,6 +131,7 @@ typedef struct PCIIORegion {
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_MASK (~0x0fUL)
+#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */