diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2014-11-01 05:28:53 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:35 +0000 |
| commit | 55a2201e79d063766509ed2f2f2e8837b9e1facf (patch) | |
| tree | b783b7a21fbb3d72d7fd01e56fba84fea8ef9b2c | |
| parent | ed8a933f977e39fc696d92f0b9f93100319a8668 (diff) | |
target-mips: add MSA support to mips32r5-generic
add MSA support to mips32r5-generic core definition
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | target-mips/translate_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a69a724d2e..4dee1caf92 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -358,7 +358,7 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), @@ -376,7 +376,7 @@ static const mips_def_t mips_defs[] = (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) |