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authorRichard Henderson <richard.henderson@linaro.org>2022-05-09 00:34:28 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-05-09 00:34:28 -0700
commit7e314198157bf38ae7fdd5a000b8795db015d582 (patch)
tree099afbbee6ffbcef6da5c346a9efe9f94ce9d264
parent554623226f800acf48a2ed568900c1c968ec9a8b (diff)
parentddc5a6cc70398ed7ec76220d59c123d8cb14b0ad (diff)
Merge tag 'pull-request-2022-05-09' of https://gitlab.com/thuth/qemu into staging
* Remove redundant/obsolete x86, arm and ppc disassemblers (Capstone is better) * Limit some Xen-related code to builds where Xen is really available * Remove hxtool-conv.pl and remove STEXI/ETEXI references from the docs * Update MinGW and OpenBSD to a more recent version in the CI * Warn user if the -vga flag is passed but no vga device is created # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmJ4s8wRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVszRAAjIJVvJgWJUlRqap/SFV3tX89jIhDKi3+ # luTBhjsDsNoFLd6ARwpykyM9dFF5sEqAHr7tjWtL7nuJIEjsnhwcUi/WUhzfkp44 # mEjmFaZL9WqXE3CD5Hd3HGhXpt5830Nmza59UvLEslLzNrmrEqQVR8cPVmmNCkG9 # diS+tata2NI1p5CF2ScxpxCfxNbDrhrhWN9cU76BM6hut1KH1oA4+fdn2QrSr610 # Y6YWvw+NlzXt9yCW2qDSUlLJvKT4VQ8r4bZ6ab/SiYzw0aHSFK14+150oyPYl91t # dN7LAyDrheZQ/R46lb76fI57kTmXRQLK0WtxK9dRJTF0hgpGgAEbMNdOOz07oQ45 # oBTFbIa7+mydgmfMZ1uZGSpUI55OOb0VE/N974MJOgXCjlFGLn0YaZezBErViBLd # ugILNle3IbZWDOwQv4n1fT3VB+2s+I1E3/qPzeDSbGAIkWm41g/4MHpkc5JGMb0j # dquDo98YdEW/gpFUSFk2u859MA/jMlla77KsOcHpBhKOvLnQtxse+Bi5If4NiR+K # NPBObMLd2j5rFtUUfDQ1fXEeAkZiITbHNR4yOiOu1tuyTm214xqMuc0/JpqWf+cr # +fd/i17j2M9Btn7EZePemuyAOqLec41QfOGid320yHS75nhBCdVkDA+g7J0MlOVF # tFBkhBJ0F+U= # =8A+p # -----END PGP SIGNATURE----- # gpg: Signature made Sun 08 May 2022 11:25:16 PM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-05-09' of https://gitlab.com/thuth/qemu: docs/devel/writing-monitor-commands: Replace obsolete STEXI/ETEXI tags Warn user if the vga flag is passed but no vga device is created tests/vm: update openbsd to release 7.1 gitlab-ci: Upgrade mingw base package. cirrus/win32: upgrade mingw base packages doc: remove hxtool-conv.pl qemu-options: Limit the -xen options to x86 and arm softmmu/vl: Fence 'xenfb' if Xen support is not compiled in disas: Remove old libopcode ppc disassembler disas: Remove old libopcode i386 disassembler disas: Remove old libopcode arm disassembler Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat
-rw-r--r--.cirrus.yml2
-rw-r--r--.gitlab-ci.d/windows.yml2
-rw-r--r--MAINTAINERS6
-rw-r--r--disas.c5
-rw-r--r--disas/arm.c4012
-rw-r--r--disas/i386.c6771
-rw-r--r--disas/meson.build3
-rw-r--r--disas/ppc.c5435
-rw-r--r--docs/devel/writing-monitor-commands.rst11
-rw-r--r--hw/hppa/machine.c1
-rw-r--r--hw/isa/isa-bus.c1
-rw-r--r--hw/mips/fuloong2e.c1
-rw-r--r--hw/pci/pci.c1
-rw-r--r--hw/ppc/spapr.c1
-rw-r--r--hw/sparc/sun4m.c2
-rw-r--r--hw/sparc64/sun4u.c1
-rw-r--r--hw/xenpv/xen_machine_pv.c1
-rw-r--r--include/disas/dis-asm.h3
-rw-r--r--include/sysemu/sysemu.h1
-rw-r--r--qemu-options.hx7
-rwxr-xr-xscripts/hxtool-conv.pl137
-rw-r--r--softmmu/globals.c1
-rw-r--r--softmmu/vl.c9
-rw-r--r--target/arm/cpu.c8
-rw-r--r--target/i386/cpu.c1
-rw-r--r--target/ppc/cpu_init.c2
-rwxr-xr-xtests/vm/openbsd4
27 files changed, 32 insertions, 16397 deletions
diff --git a/.cirrus.yml b/.cirrus.yml
index 7552d70974..20843a420c 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -12,7 +12,7 @@ windows_msys2_task:
CIRRUS_SHELL: powershell
MSYS: winsymlinks:nativestrict
MSYSTEM: MINGW64
- MSYS2_URL: https://github.com/msys2/msys2-installer/releases/download/2021-04-19/msys2-base-x86_64-20210419.sfx.exe
+ MSYS2_URL: https://github.com/msys2/msys2-installer/releases/download/2022-05-03/msys2-base-x86_64-20220503.sfx.exe
MSYS2_FINGERPRINT: 0
MSYS2_PACKAGES: "
diffutils git grep make pkg-config sed
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index 1df1630349..47f6073773 100644
--- a/.gitlab-ci.d/windows.yml
+++ b/.gitlab-ci.d/windows.yml
@@ -16,7 +16,7 @@
}
- If ( !(Test-Path -Path msys64\var\cache\msys2.exe ) ) {
Invoke-WebRequest
- "https://github.com/msys2/msys2-installer/releases/download/2021-07-25/msys2-base-x86_64-20210725.sfx.exe"
+ "https://github.com/msys2/msys2-installer/releases/download/2022-05-03/msys2-base-x86_64-20220503.sfx.exe"
-outfile "msys64\var\cache\msys2.exe"
}
- msys64\var\cache\msys2.exe -y
diff --git a/MAINTAINERS b/MAINTAINERS
index 662ec47246..aee6d623b7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -165,7 +165,6 @@ F: tests/qtest/arm-cpu-features.c
F: hw/arm/
F: hw/cpu/a*mpcore.c
F: include/hw/cpu/a*mpcore.h
-F: disas/arm.c
F: disas/arm-a64.cc
F: disas/libvixl/
F: docs/system/target-arm.rst
@@ -272,7 +271,6 @@ F: target/ppc/
F: hw/ppc/ppc.c
F: hw/ppc/ppc_booke.c
F: include/hw/ppc/ppc.h
-F: disas/ppc.c
RISC-V TCG CPUs
M: Palmer Dabbelt <palmer@dabbelt.com>
@@ -335,7 +333,6 @@ F: target/i386/tcg/
F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
-F: disas/i386.c
F: docs/system/cpu-models-x86*
T: git https://gitlab.com/ehabkost/qemu.git x86-next
@@ -3271,13 +3268,11 @@ M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained
L: qemu-arm@nongnu.org
F: tcg/arm/
-F: disas/arm.c
i386 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained
F: tcg/i386/
-F: disas/i386.c
LoongArch64 TCG target
M: WANG Xuerui <git@xen0n.name>
@@ -3297,7 +3292,6 @@ PPC TCG target
M: Richard Henderson <richard.henderson@linaro.org>
S: Odd Fixes
F: tcg/ppc/
-F: disas/ppc.c
RISC-V TCG target
M: Palmer Dabbelt <palmer@dabbelt.com>
diff --git a/disas.c b/disas.c
index d41f34915d..b2753e1902 100644
--- a/disas.c
+++ b/disas.c
@@ -153,21 +153,17 @@ static void initialize_debug_host(CPUDebug *s)
s->info.print_insn = print_insn_tci;
#elif defined(__i386__)
s->info.mach = bfd_mach_i386_i386;
- s->info.print_insn = print_insn_i386;
s->info.cap_arch = CS_ARCH_X86;
s->info.cap_mode = CS_MODE_32;
s->info.cap_insn_unit = 1;
s->info.cap_insn_split = 8;
#elif defined(__x86_64__)
s->info.mach = bfd_mach_x86_64;
- s->info.print_insn = print_insn_i386;
s->info.cap_arch = CS_ARCH_X86;
s->info.cap_mode = CS_MODE_64;
s->info.cap_insn_unit = 1;
s->info.cap_insn_split = 8;
#elif defined(_ARCH_PPC)
- s->info.disassembler_options = (char *)"any";
- s->info.print_insn = print_insn_ppc;
s->info.cap_arch = CS_ARCH_PPC;
# ifdef _ARCH_PPC64
s->info.cap_mode = CS_MODE_64;
@@ -192,7 +188,6 @@ static void initialize_debug_host(CPUDebug *s)
s->info.mach = bfd_mach_sparc_v9b;
#elif defined(__arm__)
/* TCG only generates code for arm mode. */
- s->info.print_insn = print_insn_arm;
s->info.cap_arch = CS_ARCH_ARM;
#elif defined(__MIPSEB__)
s->info.print_insn = print_insn_big_mips;
diff --git a/disas/arm.c b/disas/arm.c
deleted file mode 100644
index 7d940f2396..0000000000
--- a/disas/arm.c
+++ /dev/null
@@ -1,4012 +0,0 @@
-/* Instruction printing code for the ARM
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
- 2007, Free Software Foundation, Inc.
- Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
- Modification by James G. Smith (jsmith@cygnus.co.uk)
-
- This file is part of libopcodes.
-
- This program is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* Start of qemu specific additions. Mostly this is stub definitions
- for things we don't care about. */
-
-#include "qemu/osdep.h"
-#include "disas/dis-asm.h"
-
-#define ARM_EXT_V1 0
-#define ARM_EXT_V2 0
-#define ARM_EXT_V2S 0
-#define ARM_EXT_V3 0
-#define ARM_EXT_V3M 0
-#define ARM_EXT_V4 0
-#define ARM_EXT_V4T 0
-#define ARM_EXT_V5 0
-#define ARM_EXT_V5T 0
-#define ARM_EXT_V5ExP 0
-#define ARM_EXT_V5E 0
-#define ARM_EXT_V5J 0
-#define ARM_EXT_V6 0
-#define ARM_EXT_V6K 0
-#define ARM_EXT_V6Z 0
-#define ARM_EXT_V6T2 0
-#define ARM_EXT_V7 0
-#define ARM_EXT_DIV 0
-
-/* Co-processor space extensions. */
-#define ARM_CEXT_XSCALE 0
-#define ARM_CEXT_MAVERICK 0
-#define ARM_CEXT_IWMMXT 0
-
-#define FPU_FPA_EXT_V1 0
-#define FPU_FPA_EXT_V2 0
-#define FPU_VFP_EXT_NONE 0
-#define FPU_VFP_EXT_V1xD 0
-#define FPU_VFP_EXT_V1 0
-#define FPU_VFP_EXT_V2 0
-#define FPU_MAVERICK 0
-#define FPU_VFP_EXT_V3 0
-#define FPU_NEON_EXT_V1 0
-
-/* Assume host uses ieee float. */
-static void floatformat_to_double (unsigned char *data, double *dest)
-{
- union {
- uint32_t i;
- float f;
- } u;
- u.i = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24);
- *dest = u.f;
-}
-
-static int arm_read_memory(bfd_vma memaddr, bfd_byte *b, int length,
- struct disassemble_info *info)
-{
- assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
-
- if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
- memaddr ^= 2;
- }
- return info->read_memory_func(memaddr, b, length, info);
-}
-
-/* End of qemu specific additions. */
-
-struct opcode32
-{
- unsigned long arch; /* Architecture defining this insn. */
- unsigned long value, mask; /* Recognise insn if (op&mask)==value. */
- const char *assembler; /* How to disassemble this insn. */
-};
-
-struct opcode16
-{
- unsigned long arch; /* Architecture defining this insn. */
- unsigned short value, mask; /* Recognise insn if (op&mask)==value. */
- const char *assembler; /* How to disassemble this insn. */
-};
-
-/* print_insn_coprocessor recognizes the following format control codes:
-
- %% %
-
- %c print condition code (always bits 28-31 in ARM mode)
- %q print shifter argument
- %u print condition code (unconditional in ARM mode)
- %A print address for ldc/stc/ldf/stf instruction
- %B print vstm/vldm register list
- %C print vstr/vldr address operand
- %I print cirrus signed shift immediate: bits 0..3|4..6
- %F print the COUNT field of a LFM/SFM instruction.
- %P print floating point precision in arithmetic insn
- %Q print floating point precision in ldf/stf insn
- %R print floating point rounding mode
-
- %<bitfield>r print as an ARM register
- %<bitfield>d print the bitfield in decimal
- %<bitfield>k print immediate for VFPv3 conversion instruction
- %<bitfield>x print the bitfield in hex
- %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
- %<bitfield>f print a floating point constant if >7 else a
- floating point register
- %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
- %<bitfield>g print as an iWMMXt 64-bit register
- %<bitfield>G print as an iWMMXt general purpose or control register
- %<bitfield>D print as a NEON D register
- %<bitfield>Q print as a NEON Q register
-
- %y<code> print a single precision VFP reg.
- Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
- %z<code> print a double precision VFP reg
- Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
-
- %<bitfield>'c print specified char iff bitfield is all ones
- %<bitfield>`c print specified char iff bitfield is all zeroes
- %<bitfield>?ab... select from array of values in big endian order
-
- %L print as an iWMMXt N/M width field.
- %Z print the Immediate of a WSHUFH instruction.
- %l like 'A' except use byte offsets for 'B' & 'H'
- versions.
- %i print 5-bit immediate in bits 8,3..0
- (print "32" when 0)
- %r print register offset address for wldt/wstr instruction
-*/
-
-/* Common coprocessor opcodes shared between Arm and Thumb-2. */
-
-static const struct opcode32 coprocessor_opcodes[] =
-{
- /* XScale instructions. */
- {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
- {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
-
- /* Intel Wireless MMX technology instructions. */
-#define FIRST_IWMMXT_INSN 0x0e130130
-#define IWMMXT_INSN_COUNT 73
- {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
- {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
- {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
- {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
- {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
- {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
- {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
- {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
- {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
- {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
- {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
- {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
- {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
- {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
- {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
- {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
- {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
- {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
- {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
-
- /* Floating point coprocessor (FPA) instructions */
- {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
- {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
- {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
- {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
- {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
- {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
- {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
- {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
-
- /* Register load/store */
- {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
- {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
- {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
- {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
- {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
- {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
-
- /* Data transfer between ARM and NEON registers */
- {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
- {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
- {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
- {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
- {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
- {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
- {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
- {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
-
- /* Floating point coprocessor (VFP) instructions */
- {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
- {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
- {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
- {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
- {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
- {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"},
- {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"},
- {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
- {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
- {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
- {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
- {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
- {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
- {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
- {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
- {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
- {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
- {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
- {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
- {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
- {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
- {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
- {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
- {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
- {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
- {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
- {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
- {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
- {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
- {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
- {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
- {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
- {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
- {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
- {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
- {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
- {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
- {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
- {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
- {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
- {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
- {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
- {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
- {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
- {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
- {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
- {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
- {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
- {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
-
- /* Cirrus coprocessor instructions. */
- {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
- {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
- {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
- {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
- {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
-
- /* Generic coprocessor instructions */
- {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
-
- /* V6 coprocessor instructions */
- {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
- {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
-
- /* V5 coprocessor instructions */
- {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
-
- {0, 0, 0, 0}
-};
-
-/* Neon opcode table: This does not encode the top byte -- that is
- checked by the print_insn_neon routine, as it depends on whether we are
- doing thumb32 or arm32 disassembly. */
-
-/* print_insn_neon recognizes the following format control codes:
-
- %% %
-
- %c print condition code
- %A print v{st,ld}[1234] operands
- %B print v{st,ld}[1234] any one operands
- %C print v{st,ld}[1234] single->all operands
- %D print scalar
- %E print vmov, vmvn, vorr, vbic encoded constant
- %F print vtbl,vtbx register list
-
- %<bitfield>r print as an ARM register
- %<bitfield>d print the bitfield in decimal
- %<bitfield>e print the 2^N - bitfield in decimal
- %<bitfield>D print as a NEON D register
- %<bitfield>Q print as a NEON Q register
- %<bitfield>R print as a NEON D or Q register
- %<bitfield>Sn print byte scaled width limited by n
- %<bitfield>Tn print short scaled width limited by n
- %<bitfield>Un print long scaled width limited by n
-
- %<bitfield>'c print specified char iff bitfield is all ones
- %<bitfield>`c print specified char iff bitfield is all zeroes
- %<bitfield>?ab... select from array of values in big endian order */
-
-static const struct opcode32 neon_opcodes[] =
-{
- /* Extract */
- {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
- {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
-
- /* Move data element to all lanes */
- {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
- {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
- {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
-
- /* Table lookup */
- {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
-
- /* Two registers, miscellaneous */
- {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
- {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
- {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
- {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
- {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
- {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
- {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
-
- /* Three registers of the same length */
- {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
- {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
- {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
- {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
- {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
- {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
-
- /* One register and an immediate value */
- {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
- {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
-
- /* Two registers and a shift amount */
- {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
- {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
- {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
- {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
- {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
- {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
- {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
- {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
- {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
- {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
- {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
- {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
- {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
- {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
- {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
- {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
- {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
- {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
- {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
- {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
- {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
- {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
- {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
- {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
- {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
- {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
- {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
- {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
-
- /* Three registers of different lengths */
- {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
- {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
- {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
-
- /* Two registers and a scalar */
- {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
- {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
- {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
-
- /* Element and structure load/store */
- {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
- {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
- {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
- {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
- {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
- {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
- {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
- {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
- {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
- {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
- {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
-
- {0,0 ,0, 0}
-};
-
-/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
- ordered: they must be searched linearly from the top to obtain a correct
- match. */
-
-/* print_insn_arm recognizes the following format control codes:
-
- %% %
-
- %a print address for ldr/str instruction
- %s print address for ldr/str halfword/signextend instruction
- %b print branch destination
- %c print condition code (always bits 28-31)
- %m print register mask for ldm/stm instruction
- %o print operand2 (immediate or register + shift)
- %p print 'p' iff bits 12-15 are 15
- %t print 't' iff bit 21 set and bit 24 clear
- %B print arm BLX(1) destination
- %C print the PSR sub type.
- %U print barrier type.
- %P print address for pli instruction.
-
- %<bitfield>r print as an ARM register
- %<bitfield>d print the bitfield in decimal
- %<bitfield>W print the bitfield plus one in decimal
- %<bitfield>x print the bitfield in hex
- %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
-
- %<bitfield>'c print specified char iff bitfield is all ones
- %<bitfield>`c print specified char iff bitfield is all zeroes
- %<bitfield>?ab... select from array of values in big endian order
-
- %e print arm SMI operand (bits 0..7,8..19).
- %E print the LSB and WIDTH fields of a BFI or BFC instruction.
- %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
-
-static const struct opcode32 arm_opcodes[] =
-{
- /* ARM instructions. */
- {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
- {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
- {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
-
- /* IDIV instructions. */
- {ARM_EXT_DIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_DIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
-
- /* V7 instructions. */
- {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
- {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
- {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
- {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
- {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
-
- /* ARM V6T2 instructions. */
- {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
- {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
- {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"},
- {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"},
- {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
- {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
- {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
-
- /* ARM V6Z instructions. */
- {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
-
- /* ARM V6K instructions. */
- {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
- {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
-
- /* ARM V6K NOP hints. */
- {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
- {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
- {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
- {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
- {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
-
- /* ARM V6 instructions. */
- {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
- {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
- {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
- {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
- {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
- {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"},
- {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"},
- {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"},
- {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
- {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
- {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
- {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"},
- {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
- {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"},
- {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"},
- {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"},
- {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
- {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
- {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
- {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
- {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"},
- {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"},
- {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
- {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
- {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
- {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"},
- {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"},
- {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
-
- /* V5J instruction. */
- {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
-
- /* V5 Instructions. */
- {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
- {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
- {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
- {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
-
- /* V5E "El Segundo" Instructions. */
- {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
- {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
- {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
- {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
-
- {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
- {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
-
- {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
- {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
-
- {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
- {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
-
- /* ARM Instructions. */
- {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"},
- {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"},
- {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
- {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
- {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"},
- {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
- {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
- {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"},
- {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"},
- {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"},
- {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
- {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"},
- {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
- {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"},
- {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
- {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"},
- {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"},
- {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"},
- {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
- {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
- {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"},
- {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
- {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
- {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"},
- {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
- {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
-
- /* The rest. */
- {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
- {0, 0x00000000, 0x00000000, 0}
-};
-
-/* print_insn_thumb16 recognizes the following format control codes:
-
- %S print Thumb register (bits 3..5 as high number if bit 6 set)
- %D print Thumb register (bits 0..2 as high number if bit 7 set)
- %<bitfield>I print bitfield as a signed decimal
- (top bit of range being the sign bit)
- %N print Thumb register mask (with LR)
- %O print Thumb register mask (with PC)
- %M print Thumb register mask
- %b print CZB's 6-bit unsigned branch destination
- %s print Thumb right-shift immediate (6..10; 0 == 32).
- %c print the condition code
- %C print the condition code, or "s" if not conditional
- %x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
- %I print IT instruction suffix and operands
- %<bitfield>r print bitfield as an ARM register
- %<bitfield>d print bitfield as a decimal
- %<bitfield>H print (bitfield * 2) as a decimal
- %<bitfield>W print (bitfield * 4) as a decimal
- %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
- %<bitfield>B print Thumb branch destination (signed displacement)
- %<bitfield>c print bitfield as a condition code
- %<bitnum>'c print specified char iff bit is one
- %<bitnum>?ab print a if bit is one else print b. */
-
-static const struct opcode16 thumb_opcodes[] =
-{
- /* Thumb instructions. */
-
- /* ARM V6K no-argument instructions. */
- {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
- {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
- {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
- {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
- {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
- {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
-
- /* ARM V6T2 instructions. */
- {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
- {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
- {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
-
- /* ARM V6. */
- {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
- {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
- {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
- {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
- {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
-
- /* ARM V5 ISA extends Thumb. */
- {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
- /* This is BLX(2). BLX(1) is a 32-bit instruction. */
- {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
- /* ARM V4T ISA (Thumb v1). */
- {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
- /* Format 4. */
- {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
- {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
- /* format 13 */
- {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
- {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
- /* format 5 */
- {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
- {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
- {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
- {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
- /* format 14 */
- {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
- {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
- /* format 2 */
- {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
- {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
- {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
- {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
- /* format 8 */
- {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
- /* format 7 */
- {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
- {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
- /* format 1 */
- {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
- {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
- {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
- /* format 3 */
- {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
- {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
- /* format 6 */
- {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
- /* format 9 */
- {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
- {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
- {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
- {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
- /* format 10 */
- {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
- {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
- /* format 11 */
- {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
- {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
- /* format 12 */
- {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"},
- {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
- /* format 15 */
- {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
- {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
- /* format 17 */
- {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
- /* format 16 */
- {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
- {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
- /* format 18 */
- {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
-
- /* The E800 .. FFFF range is unconditionally redirected to the
- 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
- are processed via that table. Thus, we can never encounter a
- bare "second half of BL/BLX(1)" instruction here. */
- {ARM_EXT_V1, 0x0000, 0x0000, "undefined"},
- {0, 0, 0, 0}
-};
-
-/* Thumb32 opcodes use the same table structure as the ARM opcodes.
- We adopt the convention that hw1 is the high 16 bits of .value and
- .mask, hw2 the low 16 bits.
-
- print_insn_thumb32 recognizes the following format control codes:
-
- %% %
-
- %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
- %M print a modified 12-bit immediate (same location)
- %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
- %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
- %S print a possibly-shifted Rm
-
- %a print the address of a plain load/store
- %w print the width and signedness of a core load/store
- %m print register mask for ldm/stm
-
- %E print the lsb and width fields of a bfc/bfi instruction
- %F print the lsb and width fields of a sbfx/ubfx instruction
- %b print a conditional branch offset
- %B print an unconditional branch offset
- %s print the shift field of an SSAT instruction
- %R print the rotation field of an SXT instruction
- %U print barrier type.
- %P print address for pli instruction.
- %c print the condition code
- %x print warning if conditional an not at end of IT block"
- %X print "\t; unpredictable <IT:code>" if conditional
-
- %<bitfield>d print bitfield in decimal
- %<bitfield>W print bitfield*4 in decimal
- %<bitfield>r print bitfield as an ARM register
- %<bitfield>c print bitfield as a condition code
-
- %<bitfield>'c print specified char iff bitfield is all ones
- %<bitfield>`c print specified char iff bitfield is all zeroes
- %<bitfield>?ab... select from array of values in big endian order
-
- With one exception at the bottom (done because BL and BLX(1) need
- to come dead last), this table was machine-sorted first in
- decreasing order of number of bits set in the mask, then in
- increasing numeric order of mask, then in increasing numeric order
- of opcode. This order is not the clearest for a human reader, but
- is guaranteed never to catch a special-case bit pattern with a more
- general mask, which is important, because this instruction encoding
- makes heavy use of special-case bit patterns. */
-static const struct opcode32 thumb32_opcodes[] =
-{
- /* V7 instructions. */
- {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
- {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
- {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
- {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
- {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
- {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
-
- /* Instructions defined in the basic V6T2 set. */
- {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
- {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
- {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
- {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
- {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
- {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
-
- {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
- {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
- {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
- {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
- {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
- {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
- {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
- {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
- {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
- {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
- {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
- {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
- {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
- {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
- {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
- {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
- {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
- {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
- {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
- {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
- {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
- {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
- {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
- {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
- {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
- {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
- {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
- {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
- {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
- {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
- {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
- {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
- {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
- {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
- {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
- {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
- {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
- {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
- {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
- {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
- {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
- {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
- {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
- {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
- {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
- {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
- {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
- {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
- {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
- {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
- {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
- {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
- {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
- {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
- {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
- {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
- {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
- {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
- {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"},
- {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
- {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"},
- {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
- {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
-
- /* Filter out Bcc with cond=E or F, which are used for other instructions. */
- {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
- {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
- {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
- {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
-
- /* These have been 32-bit since the invention of Thumb. */
- {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"},
- {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
-
- /* Fallback. */
- {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"},
- {0, 0, 0, 0}
-};
-
-static const char *const arm_conditional[] =
-{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
- "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
-
-static const char *const arm_fp_const[] =
-{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
-
-static const char *const arm_shift[] =
-{"lsl", "lsr", "asr", "ror"};
-
-typedef struct
-{
- const char *name;
- const char *description;
- const char *reg_names[16];
-}
-arm_regname;
-
-static const arm_regname regnames[] =
-{
- { "raw" , "Select raw register names",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
- { "gcc", "Select register names used by GCC",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "std", "Select register names used in ARM's ISA documentation",
- { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
- { "apcs", "Select register names used in the APCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
- { "atpcs", "Select register names used in the ATPCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
- { "special-atpcs", "Select special register names used in the ATPCS",
- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
-};
-
-static const char *const iwmmxt_wwnames[] =
-{"b", "h", "w", "d"};
-
-static const char *const iwmmxt_wwssnames[] =
-{"b", "bus", "bc", "bss",
- "h", "hus", "hc", "hss",
- "w", "wus", "wc", "wss",
- "d", "dus", "dc", "dss"
-};
-
-static const char *const iwmmxt_regnames[] =
-{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
- "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
-};
-
-static const char *const iwmmxt_cregnames[] =
-{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
- "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
-};
-
-/* Default to GCC register name set. */
-static unsigned int regname_selected = 1;
-
-#define arm_regnames regnames[regname_selected].reg_names
-
-static bfd_boolean force_thumb = false;
-
-/* Current IT instruction state. This contains the same state as the IT
- bits in the CPSR. */
-static unsigned int ifthen_state;
-/* IT state for the next instruction. */
-static unsigned int ifthen_next_state;
-/* The address of the insn for which the IT state is valid. */
-static bfd_vma ifthen_address;
-#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
-
-/* Cached mapping symbol state. */
-enum map_type {
- MAP_ARM,
- MAP_THUMB,
- MAP_DATA
-};
-
-/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
- Returns pointer to following character of the format string and
- fills in *VALUEP and *WIDTHP with the extracted value and number of
- bits extracted. WIDTHP can be NULL. */
-
-static const char *
-arm_decode_bitfield (const char *ptr, unsigned long insn,
- unsigned long *valuep, int *widthp)
-{
- unsigned long value = 0;
- int width = 0;
-
- do
- {
- int start, end;
- int bits;
-
- for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
- start = start * 10 + *ptr - '0';
- if (*ptr == '-')
- for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
- end = end * 10 + *ptr - '0';
- else
- end = start;
- bits = end - start;
- if (bits < 0)
- abort ();
- value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
- width += bits + 1;
- }
- while (*ptr++ == ',');
- *valuep = value;
- if (widthp)
- *widthp = width;
- return ptr - 1;
-}
-
-static void
-arm_decode_shift (long given, fprintf_function func, void *stream,
- int print_shift)
-{
- func (stream, "%s", arm_regnames[given & 0xf]);
-
- if ((given & 0xff0) != 0)
- {
- if ((given & 0x10) == 0)
- {
- int amount = (given & 0xf80) >> 7;
- int shift = (given & 0x60) >> 5;
-
- if (amount == 0)
- {
- if (shift == 3)
- {
- func (stream, ", rrx");
- return;
- }
-
- amount = 32;
- }
-
- if (print_shift)
- func (stream, ", %s #%d", arm_shift[shift], amount);
- else
- func (stream, ", #%d", amount);
- }
- else if (print_shift)
- func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
- arm_regnames[(given & 0xf00) >> 8]);
- else
- func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
- }
-}
-
-/* Print one coprocessor instruction on INFO->STREAM.
- Return true if the instruction matched, false if this is not a
- recognised coprocessor instruction. */
-
-static bfd_boolean
-print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
- bfd_boolean thumb)
-{
- const struct opcode32 *insn;
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
- unsigned long mask;
- unsigned long value;
- int cond;
-
- for (insn = coprocessor_opcodes; insn->assembler; insn++)
- {
- if (insn->value == FIRST_IWMMXT_INSN
- && info->mach != bfd_mach_arm_XScale
- && info->mach != bfd_mach_arm_iWMMXt
- && info->mach != bfd_mach_arm_iWMMXt2)
- insn = insn + IWMMXT_INSN_COUNT;
-
- mask = insn->mask;
- value = insn->value;
- if (thumb)
- {
- /* The high 4 bits are 0xe for Arm conditional instructions, and
- 0xe for arm unconditional instructions. The rest of the
- encoding is the same. */
- mask |= 0xf0000000;
- value |= 0xe0000000;
- if (ifthen_state)
- cond = IFTHEN_COND;
- else
- cond = 16;
- }
- else
- {
- /* Only match unconditional instructions against unconditional
- patterns. */
- if ((given & 0xf0000000) == 0xf0000000)
- {
- mask |= 0xf0000000;
- cond = 16;
- }
- else
- {
- cond = (given >> 28) & 0xf;
- if (cond == 0xe)
- cond = 16;
- }
- }
- if ((given & mask) == value)
- {
- const char *c;
-
- for (c = insn->assembler; *c; c++)
- {
- if (*c == '%')
- {
- switch (*++c)
- {
- case '%':
- func (stream, "%%");
- break;
-
- case 'A':
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
-
- if ((given & (1 << 24)) != 0)
- {
- int offset = given & 0xff;
-
- if (offset)
- func (stream, ", #%s%d]%s",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * 4,
- ((given & 0x00200000) != 0 ? "!" : ""));
- else
- func (stream, "]");
- }
- else
- {
- int offset = given & 0xff;
-
- func (stream, "]");
-
- if (given & (1 << 21))
- {
- if (offset)
- func (stream, ", #%s%d",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * 4);
- }
- else
- func (stream, ", {%d}", offset);
- }
- break;
-
- case 'B':
- {
- int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
- int offset = (given >> 1) & 0x3f;
-
- if (offset == 1)
- func (stream, "{d%d}", regno);
- else if (regno + offset > 32)
- func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
- else
- func (stream, "{d%d-d%d}", regno, regno + offset - 1);
- }
- break;
-
- case 'C':
- {
- int rn = (given >> 16) & 0xf;
- int offset = (given & 0xff) * 4;
- int add = (given >> 23) & 1;
-
- func (stream, "[%s", arm_regnames[rn]);
-
- if (offset)
- {
- if (!add)
- offset = -offset;
- func (stream, ", #%d", offset);
- }
- func (stream, "]");
- if (rn == 15)
- {
- func (stream, "\t; ");
- /* FIXME: Unsure if info->bytes_per_chunk is the
- right thing to use here. */
- info->print_address_func (offset + pc
- + info->bytes_per_chunk * 2, info);
- }
- }
- break;
-
- case 'c':
- func (stream, "%s", arm_conditional[cond]);
- break;
-
- case 'I':
- /* Print a Cirrus/DSP shift immediate. */
- /* Immediates are 7bit signed ints with bits 0..3 in
- bits 0..3 of opcode and bits 4..6 in bits 5..7
- of opcode. */
- {
- int imm;
-
- imm = (given & 0xf) | ((given & 0xe0) >> 1);
-
- /* Is ``imm'' a negative number? */
- if (imm & 0x40)
- imm |= (~0u << 7);
-
- func (stream, "%d", imm);
- }
-
- break;
-
- case 'F':
- switch (given & 0x00408000)
- {
- case 0:
- func (stream, "4");
- break;
- case 0x8000:
- func (stream, "1");
- break;
- case 0x00400000:
- func (stream, "2");
- break;
- default:
- func (stream, "3");
- }
- break;
-
- case 'P':
- switch (given & 0x00080080)
- {
- case 0:
- func (stream, "s");
- break;
- case 0x80:
- func (stream, "d");
- break;
- case 0x00080000:
- func (stream, "e");
- break;
- default:
- func (stream, "<illegal precision>");
- break;
- }
- break;
- case 'Q':
- switch (given & 0x00408000)
- {
- case 0:
- func (stream, "s");
- break;
- case 0x8000:
- func (stream, "d");
- break;
- case 0x00400000:
- func (stream, "e");
- break;
- default:
- func (stream, "p");
- break;
- }
- break;
- case 'R':
- switch (given & 0x60)
- {
- case 0:
- break;
- case 0x20:
- func (stream, "p");
- break;
- case 0x40:
- func (stream, "m");
- break;
- default:
- func (stream, "z");
- break;
- }
- break;
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- {
- int width;
- unsigned long value;
-
- c = arm_decode_bitfield (c, given, &value, &width);
-
- switch (*c)
- {
- case 'r':
- func (stream, "%s", arm_regnames[value]);
- break;
- case 'D':
- func (stream, "d%ld", value);
- break;
- case 'Q':
- if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
- else
- func (stream, "q%ld", value >> 1);
- break;
- case 'd':
- func (stream, "%ld", value);
- break;
- case 'k':
- {
- int from = (given & (1 << 7)) ? 32 : 16;
- func (stream, "%ld", from - value);
- }
- break;
-
- case 'f':
- if (value > 7)
- func (stream, "#%s", arm_fp_const[value & 7]);
- else
- func (stream, "f%ld", value);
- break;
-
- case 'w':
- if (width == 2)
- func (stream, "%s", iwmmxt_wwnames[value]);
- else
- func (stream, "%s", iwmmxt_wwssnames[value]);
- break;
-
- case 'g':
- func (stream, "%s", iwmmxt_regnames[value]);
- break;
- case 'G':
- func (stream, "%s", iwmmxt_cregnames[value]);
- break;
-
- case 'x':
- func (stream, "0x%lx", value);
- break;
-
- case '`':
- c++;
- if (value == 0)
- func (stream, "%c", *c);
- break;
- case '\'':
- c++;
- if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
- break;
- case '?':
- func (stream, "%c", c[(1 << width) - (int)value]);
- c += 1 << width;
- break;
- default:
- abort ();
- }
- break;
-
- case 'y':
- case 'z':
- {
- int single = *c++ == 'y';
- int regno;
-
- switch (*c)
- {
- case '4': /* Sm pair */
- func (stream, "{");
- /* Fall through. */
- case '0': /* Sm, Dm */
- regno = given & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 5) & 1;
- }
- else
- regno += ((given >> 5) & 1) << 4;
- break;
-
- case '1': /* Sd, Dd */
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
-
- case '2': /* Sn, Dn */
- regno = (given >> 16) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 7) & 1;
- }
- else
- regno += ((given >> 7) & 1) << 4;
- break;
-
- case '3': /* List */
- func (stream, "{");
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
-
- default:
- abort ();
- }
-
- func (stream, "%c%d", single ? 's' : 'd', regno);
-
- if (*c == '3')
- {
- int count = given & 0xff;
-
- if (single == 0)
- count >>= 1;
-
- if (--count)
- {
- func (stream, "-%c%d",
- single ? 's' : 'd',
- regno + count);
- }
-
- func (stream, "}");
- }
- else if (*c == '4')
- func (stream, ", %c%d}", single ? 's' : 'd',
- regno + 1);
- }
- break;
-
- case 'L':
- switch (given & 0x00400100)
- {
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
- default:
- break;
- }
- break;
-
- case 'Z':
- {
- int value;
- /* given (20, 23) | given (0, 3) */
- value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", value);
- }
- break;
-
- case 'l':
- /* This is like the 'A' operator, except that if
- the width field "M" is zero, then the offset is
- *not* multiplied by four. */
- {
- int offset = given & 0xff;
- int multiplier = (given & 0x00000100) ? 4 : 1;
-
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
-
- if (offset)
- {
- if ((given & 0x01000000) != 0)
- func (stream, ", #%s%d]%s",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * multiplier,
- ((given & 0x00200000) != 0 ? "!" : ""));
- else
- func (stream, "], #%s%d",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * multiplier);
- }
- else
- func (stream, "]");
- }
- break;
-
- case 'r':
- {
- int imm4 = (given >> 4) & 0xf;
- int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
- int ubit = (given >> 23) & 1;
- const char *rm = arm_regnames [given & 0xf];
- const char *rn = arm_regnames [(given >> 16) & 0xf];
-
- switch (puw_bits)
- {
- case 1:
- /* fall through */
- case 3:
- func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4)
- func (stream, ", lsl #%d", imm4);
- break;
-
- case 4:
- /* fall through */
- case 5:
- /* fall through */
- case 6:
- /* fall through */
- case 7:
- func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4 > 0)
- func (stream, ", lsl #%d", imm4);
- func (stream, "]");
- if (puw_bits == 5 || puw_bits == 7)
- func (stream, "!");
- break;
-
- default:
- func (stream, "INVALID");
- }
- }
- break;
-
- case 'i':
- {
- long imm5;
- imm5 = ((given & 0x100) >> 4) | (given & 0xf);
- func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
- }
- break;
-
- default:
- abort ();
- }
- }
- }
- else
- func (stream, "%c", *c);
- }
- return true;
- }
- }
- return false;
-}
-
-static void
-print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
-{
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
-
- if (((given & 0x000f0000) == 0x000f0000)
- && ((given & 0x02000000) == 0))
- {
- int offset = given & 0xfff;
-
- func (stream, "[pc");
-
- if (given & 0x01000000)
- {
- if ((given & 0x00800000) == 0)
- offset = - offset;
-
- /* Pre-indexed. */
- func (stream, ", #%d]", offset);
-
- offset += pc + 8;
-
- /* Cope with the possibility of write-back
- being used. Probably a very dangerous thing
- for the programmer to do, but who are we to
- argue ? */
- if (given & 0x00200000)
- func (stream, "!");
- }
- else
- {
- /* Post indexed. */
- func (stream, "], #%d", offset);
-
- /* ie ignore the offset. */
- offset = pc + 8;
- }
-
- func (stream, "\t; ");
- info->print_address_func (offset, info);
- }
- else
- {
- func (stream, "[%s",
- arm_regnames[(given >> 16) & 0xf]);
- if ((given & 0x01000000) != 0)
- {
- if ((given & 0x02000000) == 0)
- {
- int offset = given & 0xfff;
- if (offset)
- func (stream, ", #%s%d",
- (((given & 0x00800000) == 0)
- ? "-" : ""), offset);
- }
- else
- {
- func (stream, ", %s",
- (((given & 0x00800000) == 0)
- ? "-" : ""));
- arm_decode_shift (given, func, stream, 1);
- }
-
- func (stream, "]%s",
- ((given & 0x00200000) != 0) ? "!" : "");
- }
- else
- {
- if ((given & 0x02000000) == 0)
- {
- int offset = given & 0xfff;
- if (offset)
- func (stream, "], #%s%d",
- (((given & 0x00800000) == 0)
- ? "-" : ""), offset);
- else
- func (stream, "]");
- }
- else
- {
- func (stream, "], %s",
- (((given & 0x00800000) == 0)
- ? "-" : ""));
- arm_decode_shift (given, func, stream, 1);
- }
- }
- }
-}
-
-/* Print one neon instruction on INFO->STREAM.
- Return true if the instruction matched, false if this is not a
- recognised neon instruction. */
-
-static bfd_boolean
-print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
-{
- const struct opcode32 *insn;
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
-
- if (thumb)
- {
- if ((given & 0xef000000) == 0xef000000)
- {
- /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
- unsigned long bit28 = given & (1 << 28);
-
- given &= 0x00ffffff;
- if (bit28)
- given |= 0xf3000000;
- else
- given |= 0xf2000000;
- }
- else if ((given & 0xff000000) == 0xf9000000)
- given ^= 0xf9000000 ^ 0xf4000000;
- else
- return false;
- }
-
- for (insn = neon_opcodes; insn->assembler; insn++)
- {
- if ((given & insn->mask) == insn->value)
- {
- const char *c;
-
- for (c = insn->assembler; *c; c++)
- {
- if (*c == '%')
- {
- switch (*++c)
- {
- case '%':
- func (stream, "%%");
- break;
-
- case 'c':
- if (thumb && ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
- break;
-
- case 'A':
- {
- static const unsigned char enc[16] =
- {
- 0x4, 0x14, /* st4 0,1 */
- 0x4, /* st1 2 */
- 0x4, /* st2 3 */
- 0x3, /* st3 4 */
- 0x13, /* st3 5 */
- 0x3, /* st1 6 */
- 0x1, /* st1 7 */
- 0x2, /* st2 8 */
- 0x12, /* st2 9 */
- 0x2, /* st1 10 */
- 0, 0, 0, 0, 0
- };
- int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
- int rn = ((given >> 16) & 0xf);
- int rm = ((given >> 0) & 0xf);
- int align = ((given >> 4) & 0x3);
- int type = ((given >> 8) & 0xf);
- int n = enc[type] & 0xf;
- int stride = (enc[type] >> 4) + 1;
- int ix;
-
- func (stream, "{");
- if (stride > 1)
- for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
- else if (n == 1)
- func (stream, "d%d", rd);
- else
- func (stream, "d%d-d%d", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
- if (align)
- func (stream, ", :%d", 32 << align);
- func (stream, "]");
- if (rm == 0xd)
- func (stream, "!");
- else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
- }
- break;
-
- case 'B':
- {
- int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
- int rn = ((given >> 16) & 0xf);
- int rm = ((given >> 0) & 0xf);
- int idx_align = ((given >> 4) & 0xf);
- int align = 0;
- int size = ((given >> 10) & 0x3);
- int idx = idx_align >> (size + 1);
- int length = ((given >> 8) & 3) + 1;
- int stride = 1;
- int i;
-
- if (length > 1 && size > 0)
- stride = (idx_align & (1 << size)) ? 2 : 1;
-
- switch (length)
- {
- case 1:
- {
- int amask = (1 << size) - 1;
- if ((idx_align & (1 << size)) != 0)
- return false;
- if (size > 0)
- {
- if ((idx_align & amask) == amask)
- align = 8 << size;
- else if ((idx_align & amask) != 0)
- return false;
- }
- }
- break;
-
- case 2:
- if (size == 2 && (idx_align & 2) != 0)
- return false;
- align = (idx_align & 1) ? 16 << size : 0;
- break;
-
- case 3:
- if ((size == 2 && (idx_align & 3) != 0)
- || (idx_align & 1) != 0)
- return false;
- break;
-
- case 4:
- if (size == 2)
- {
- if ((idx_align & 3) == 3)
- return false;
- align = (idx_align & 3) * 64;
- }
- else
- align = (idx_align & 1) ? 32 << size : 0;
- break;
-
- default:
- abort ();
- }
-
- func (stream, "{");
- for (i = 0; i < length; i++)
- func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
- rd + i * stride, idx);
- func (stream, "}, [%s", arm_regnames[rn]);
- if (align)
- func (stream, ", :%d", align);
- func (stream, "]");
- if (rm == 0xd)
- func (stream, "!");
- else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
- }
- break;
-
- case 'C':
- {
- int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
- int rn = ((given >> 16) & 0xf);
- int rm = ((given >> 0) & 0xf);
- int align = ((given >> 4) & 0x1);
- int size = ((given >> 6) & 0x3);
- int type = ((given >> 8) & 0x3);
- int n = type + 1;
- int stride = ((given >> 5) & 0x1);
- int ix;
-
- if (stride && (n == 1))
- n++;
- else
- stride++;
-
- func (stream, "{");
- if (stride > 1)
- for (ix = 0; ix != n; ix++)
- func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
- else if (n == 1)
- func (stream, "d%d[]", rd);
- else
- func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
- func (stream, "}, [%s", arm_regnames[rn]);
- if (align)
- {
- int align = (8 * (type + 1)) << size;
- if (type == 3)
- align = (size > 1) ? align >> 1 : align;
- if (type == 2 || (type == 0 && !size))
- func (stream, ", :<bad align %d>", align);
- else
- func (stream, ", :%d", align);
- }
- func (stream, "]");
- if (rm == 0xd)
- func (stream, "!");
- else if (rm != 0xf)
- func (stream, ", %s", arm_regnames[rm]);
- }
- break;
-
- case 'D':
- {
- int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
- int size = (given >> 20) & 3;
- int reg = raw_reg & ((4 << size) - 1);
- int ix = raw_reg >> size >> 2;
-
- func (stream, "d%d[%d]", reg, ix);
- }
- break;
-
- case 'E':
- /* Neon encoded constant for mov, mvn, vorr, vbic */
- {
- int bits = 0;
- int cmode = (given >> 8) & 0xf;
- int op = (given >> 5) & 0x1;
- unsigned long value = 0, hival = 0;
- unsigned shift;
- int size = 0;
- int isfloat = 0;
-
- bits |= ((given >> 24) & 1) << 7;
- bits |= ((given >> 16) & 7) << 4;
- bits |= ((given >> 0) & 15) << 0;
-
- if (cmode < 8)
- {
- shift = (cmode >> 1) & 3;
- value = (unsigned long)bits << (8 * shift);
- size = 32;
- }
- else if (cmode < 12)
- {
- shift = (cmode >> 1) & 1;
- value = (unsigned long)bits << (8 * shift);
- size = 16;
- }
- else if (cmode < 14)
- {
- shift = (cmode & 1) + 1;
- value = (unsigned long)bits << (8 * shift);
- value |= (1ul << (8 * shift)) - 1;
- size = 32;
- }
- else if (cmode == 14)
- {
- if (op)
- {
- /* bit replication into bytes */
- int ix;
- unsigned long mask;
-
- value = 0;
- hival = 0;
- for (ix = 7; ix >= 0; ix--)
- {
- mask = ((bits >> ix) & 1) ? 0xff : 0;
- if (ix <= 3)
- value = (value << 8) | mask;
- else
- hival = (hival << 8) | mask;
- }
- size = 64;
- }
- else
- {
- /* byte replication */
- value = (unsigned long)bits;
- size = 8;
- }
- }
- else if (!op)
- {
- /* floating point encoding */
- int tmp;
-
- value = (unsigned long)(bits & 0x7f) << 19;
- value |= (unsigned long)(bits & 0x80) << 24;
- tmp = bits & 0x40 ? 0x3c : 0x40;
- value |= (unsigned long)tmp << 24;
- size = 32;
- isfloat = 1;
- }
- else
- {
- func (stream, "<illegal constant %.8x:%x:%x>",
- bits, cmode, op);
- break;
- }
- switch (size)
- {
- case 8:
- func (stream, "#%ld\t; 0x%.2lx", value, value);
- break;
-
- case 16:
- func (stream, "#%ld\t; 0x%.4lx", value, value);
- break;
-
- case 32:
- if (isfloat)
- {
- unsigned char valbytes[4];
- double fvalue;
-
- /* Do this a byte at a time so we don't have to
- worry about the host's endianness. */
- valbytes[0] = value & 0xff;
- valbytes[1] = (value >> 8) & 0xff;
- valbytes[2] = (value >> 16) & 0xff;
- valbytes[3] = (value >> 24) & 0xff;
-
- floatformat_to_double (valbytes, &fvalue);
-
- func (stream, "#%.7g\t; 0x%.8lx", fvalue,
- value);
- }
- else
- func (stream, "#%ld\t; 0x%.8lx",
- (long) ((value & 0x80000000)
- ? value | ~0xffffffffl : value), value);
- break;
-
- case 64:
- func (stream, "#0x%.8lx%.8lx", hival, value);
- break;
-
- default:
- abort ();
- }
- }
- break;
-
- case 'F':
- {
- int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
- int num = (given >> 8) & 0x3;
-
- if (!num)
- func (stream, "{d%d}", regno);
- else if (num + regno >= 32)
- func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
- else
- func (stream, "{d%d-d%d}", regno, regno + num);
- }
- break;
-
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- {
- int width;
- unsigned long value;
-
- c = arm_decode_bitfield (c, given, &value, &width);
-
- switch (*c)
- {
- case 'r':
- func (stream, "%s", arm_regnames[value]);
- break;
- case 'd':
- func (stream, "%ld", value);
- break;
- case 'e':
- func (stream, "%ld", (1ul << width) - value);
- break;
-
- case 'S':
- case 'T':
- case 'U':
- /* various width encodings */
- {
- int base = 8 << (*c - 'S'); /* 8,16 or 32 */
- int limit;
- unsigned low, high;
-
- c++;
- if (*c >= '0' && *c <= '9')
- limit = *c - '0';
- else if (*c >= 'a' && *c <= 'f')
- limit = *c - 'a' + 10;
- else
- abort ();
- low = limit >> 2;
- high = limit & 3;
-
- if (value < low || value > high)
- func (stream, "<illegal width %d>", base << value);
- else
- func (stream, "%d", base << value);
- }
- break;
- case 'R':
- if (given & (1 << 6))
- goto Q;
- /* FALLTHROUGH */
- case 'D':
- func (stream, "d%ld", value);
- break;
- case 'Q':
- Q:
- if (value & 1)
- func (stream, "<illegal reg q%ld.5>", value >> 1);
- else
- func (stream, "q%ld", value >> 1);
- break;
-
- case '`':
- c++;
- if (value == 0)
- func (stream, "%c", *c);
- break;
- case '\'':
- c++;
- if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
- break;
- case '?':
- func (stream, "%c", c[(1 << width) - (int)value]);
- c += 1 << width;
- break;
- default:
- abort ();
- }
- break;
-
- default:
- abort ();
- }
- }
- }
- else
- func (stream, "%c", *c);
- }
- return true;
- }
- }
- return false;
-}
-
-/* Print one ARM instruction from PC on INFO->STREAM. */
-
-static void
-print_insn_arm_internal (bfd_vma pc, struct disassemble_info *info, long given)
-{
- const struct opcode32 *insn;
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
-
- if (print_insn_coprocessor (pc, info, given, false))
- return;
-
- if (print_insn_neon (info, given, false))
- return;
-
- for (insn = arm_opcodes; insn->assembler; insn++)
- {
- if (insn->value == FIRST_IWMMXT_INSN
- && info->mach != bfd_mach_arm_XScale
- && info->mach != bfd_mach_arm_iWMMXt)
- insn = insn + IWMMXT_INSN_COUNT;
-
- if ((given & insn->mask) == insn->value
- /* Special case: an instruction with all bits set in the condition field
- (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
- or by the catchall at the end of the table. */
- && ((given & 0xF0000000) != 0xF0000000
- || (insn->mask & 0xF0000000) == 0xF0000000
- || (insn->mask == 0 && insn->value == 0)))
- {
- const char *c;
-
- for (c = insn->assembler; *c; c++)
- {
- if (*c == '%')
- {
- switch (*++c)
- {
- case '%':
- func (stream, "%%");
- break;
-
- case 'a':
- print_arm_address (pc, info, given);
- break;
-
- case 'P':
- /* Set P address bit and use normal address
- printing routine. */
- print_arm_address (pc, info, given | (1 << 24));
- break;
-
- case 's':
- if ((given & 0x004f0000) == 0x004f0000)
- {
- /* PC relative with immediate offset. */
- int offset = ((given & 0xf00) >> 4) | (given & 0xf);
-
- if ((given & 0x00800000) == 0)
- offset = -offset;
-
- func (stream, "[pc, #%d]\t; ", offset);
- info->print_address_func (offset + pc + 8, info);
- }
- else
- {
- func (stream, "[%s",
- arm_regnames[(given >> 16) & 0xf]);
- if ((given & 0x01000000) != 0)
- {
- /* Pre-indexed. */
- if ((given & 0x00400000) == 0x00400000)
- {
- /* Immediate. */
- int offset = ((given & 0xf00) >> 4) | (given & 0xf);
- if (offset)
- func (stream, ", #%s%d",
- (((given & 0x00800000) == 0)
- ? "-" : ""), offset);
- }
- else
- {
- /* Register. */
- func (stream, ", %s%s",
- (((given & 0x00800000) == 0)
- ? "-" : ""),
- arm_regnames[given & 0xf]);
- }
-
- func (stream, "]%s",
- ((given & 0x00200000) != 0) ? "!" : "");
- }
- else
- {
- /* Post-indexed. */
- if ((given & 0x00400000) == 0x00400000)
- {
- /* Immediate. */
- int offset = ((given & 0xf00) >> 4) | (given & 0xf);
- if (offset)
- func (stream, "], #%s%d",
- (((given & 0x00800000) == 0)
- ? "-" : ""), offset);
- else
- func (stream, "]");
- }
- else
- {
- /* Register. */
- func (stream, "], %s%s",
- (((given & 0x00800000) == 0)
- ? "-" : ""),
- arm_regnames[given & 0xf]);
- }
- }
- }
- break;
-
- case 'b':
- {
- int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
- info->print_address_func (disp*4 + pc + 8, info);
- }
- break;
-
- case 'c':
- if (((given >> 28) & 0xf) != 0xe)
- func (stream, "%s",
- arm_conditional [(given >> 28) & 0xf]);
- break;
-
- case 'm':
- {
- int started = 0;
- int reg;
-
- func (stream, "{");
- for (reg = 0; reg < 16; reg++)
- if ((given & (1 << reg)) != 0)
- {
- if (started)
- func (stream, ", ");
- started = 1;
- func (stream, "%s", arm_regnames[reg]);
- }
- func (stream, "}");
- }
- break;
-
- case 'q':
- arm_decode_shift (given, func, stream, 0);
- break;
-
- case 'o':
- if ((given & 0x02000000) != 0)
- {
- int rotate = (given & 0xf00) >> 7;
- int immed = (given & 0xff);
- immed = (((immed << (32 - rotate))
- | (immed >> rotate)) & 0xffffffff);
- func (stream, "#%d\t; 0x%x", immed, immed);
- }
- else
- arm_decode_shift (given, func, stream, 1);
- break;
-
- case 'p':
- if ((given & 0x0000f000) == 0x0000f000)
- func (stream, "p");
- break;
-
- case 't':
- if ((given & 0x01200000) == 0x00200000)
- func (stream, "t");
- break;
-
- case 'A':
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
-
- if ((given & (1 << 24)) != 0)
- {
- int offset = given & 0xff;
-
- if (offset)
- func (stream, ", #%s%d]%s",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * 4,
- ((given & 0x00200000) != 0 ? "!" : ""));
- else
- func (stream, "]");
- }
- else
- {
- int offset = given & 0xff;
-
- func (stream, "]");
-
- if (given & (1 << 21))
- {
- if (offset)
- func (stream, ", #%s%d",
- ((given & 0x00800000) == 0 ? "-" : ""),
- offset * 4);
- }
- else
- func (stream, ", {%d}", offset);
- }
- break;
-
- case 'B':
- /* Print ARM V5 BLX(1) address: pc+25 bits. */
- {
- bfd_vma address;
- bfd_vma offset = 0;
-
- if (given & 0x00800000)
- /* Is signed, hi bits should be ones. */
- offset = (-1) ^ 0x00ffffff;
-
- /* Offset is (SignExtend(offset field)<<2). */
- offset += given & 0x00ffffff;
- offset <<= 2;
- address = offset + pc + 8;
-
- if (given & 0x01000000)
- /* H bit allows addressing to 2-byte boundaries. */
- address += 2;
-
- info->print_address_func (address, info);
- }
- break;
-
- case 'C':
- func (stream, "_");
- if (given & 0x80000)
- func (stream, "f");
- if (given & 0x40000)
- func (stream, "s");
- if (given & 0x20000)
- func (stream, "x");
- if (given & 0x10000)
- func (stream, "c");
- break;
-
- case 'U':
- switch (given & 0xf)
- {
- case 0xf: func(stream, "sy"); break;
- case 0x7: func(stream, "un"); break;
- case 0xe: func(stream, "st"); break;
- case 0x6: func(stream, "unst"); break;
- default:
- func(stream, "#%d", (int)given & 0xf);
- break;
- }
- break;
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- {
- int width;
- unsigned long value;
-
- c = arm_decode_bitfield (c, given, &value, &width);
-
- switch (*c)
- {
- case 'r':
- func (stream, "%s", arm_regnames[value]);
- break;
- case 'd':
- func (stream, "%ld", value);
- break;
- case 'b':
- func (stream, "%ld", value * 8);
- break;
- case 'W':
- func (stream, "%ld", value + 1);
- break;
- case 'x':
- func (stream, "0x%08lx", value);
-
- /* Some SWI instructions have special
- meanings. */
- if ((given & 0x0fffffff) == 0x0FF00000)
- func (stream, "\t; IMB");
- else if ((given & 0x0fffffff) == 0x0FF00001)
- func (stream, "\t; IMBRange");
- break;
- case 'X':
- func (stream, "%01lx", value & 0xf);
- break;
- case '`':
- c++;
- if (value == 0)
- func (stream, "%c", *c);
- break;
- case '\'':
- c++;
- if (value == ((1ul << width) - 1))
- func (stream, "%c", *c);
- break;
- case '?':
- func (stream, "%c", c[(1 << width) - (int)value]);
- c += 1 << width;
- break;
- default:
- abort ();
- }
- break;
-
- case 'e':
- {
- int imm;
-
- imm = (given & 0xf) | ((given & 0xfff00) >> 4);
- func (stream, "%d", imm);
- }
- break;
-
- case 'E':
- /* LSB and WIDTH fields of BFI or BFC. The machine-
- language instruction encodes LSB and MSB. */
- {
- long msb = (given & 0x001f0000) >> 16;
- long lsb = (given & 0x00000f80) >> 7;
-
- long width = msb - lsb + 1;
- if (width > 0)
- func (stream, "#%lu, #%lu", lsb, width);
- else
- func (stream, "(invalid: %lu:%lu)", lsb, msb);
- }
- break;
-
- case 'V':
- /* 16-bit unsigned immediate from a MOVT or MOVW
- instruction, encoded in bits 0:11 and 15:19. */
- {
- long hi = (given & 0x000f0000) >> 4;
- long lo = (given & 0x00000fff);
- long imm16 = hi | lo;
- func (stream, "#%lu\t; 0x%lx", imm16, imm16);
- }
- break;
-
- default:
- abort ();
- }
- }
- }
- else
- func (stream, "%c", *c);
- }
- return;
- }
- }
- abort ();
-}
-
-/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
-
-static void
-print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
-{
- const struct opcode16 *insn;
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
-
- for (insn = thumb_opcodes; insn->assembler; insn++)
- if ((given & insn->mask) == insn->value)
- {
- const char *c = insn->assembler;
- for (; *c; c++)
- {
- int domaskpc = 0;
- int domasklr = 0;
-
- if (*c != '%')
- {
- func (stream, "%c", *c);
- continue;
- }
-
- switch (*++c)
- {
- case '%':
- func (stream, "%%");
- break;
-
- case 'c':
- if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
- break;
-
- case 'C':
- if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
- else
- func (stream, "s");
- break;
-
- case 'I':
- {
- unsigned int tmp;
-
- ifthen_next_state = given & 0xff;
- for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
- func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
- func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
- }
- break;
-
- case 'x':
- if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
- break;
-
- case 'X':
- if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
- arm_conditional[IFTHEN_COND]);
- break;
-
- case 'S':
- {
- long reg;
-
- reg = (given >> 3) & 0x7;
- if (given & (1 << 6))
- reg += 8;
-
- func (stream, "%s", arm_regnames[reg]);
- }
- break;
-
- case 'D':
- {
- long reg;
-
- reg = given & 0x7;
- if (given & (1 << 7))
- reg += 8;
-
- func (stream, "%s", arm_regnames[reg]);
- }
- break;
-
- case 'N':
- if (given & (1 << 8))
- domasklr = 1;
- /* Fall through. */
- case 'O':
- if (*c == 'O' && (given & (1 << 8)))
- domaskpc = 1;
- /* Fall through. */
- case 'M':
- {
- int started = 0;
- int reg;
-
- func (stream, "{");
-
- /* It would be nice if we could spot
- ranges, and generate the rS-rE format: */
- for (reg = 0; (reg < 8); reg++)
- if ((given & (1 << reg)) != 0)
- {
- if (started)
- func (stream, ", ");
- started = 1;
- func (stream, "%s", arm_regnames[reg]);
- }
-
- if (domasklr)
- {
- if (started)
- func (stream, ", ");
- started = 1;
- func (stream, "%s", arm_regnames[14] /* "lr" */);
- }
-
- if (domaskpc)
- {
- if (started)
- func (stream, ", ");
- func (stream, "%s", arm_regnames[15] /* "pc" */);
- }
-
- func (stream, "}");
- }
- break;
-
- case 'b':
- /* Print ARM V6T2 CZB address: pc+4+6 bits. */
- {
- bfd_vma address = (pc + 4
- + ((given & 0x00f8) >> 2)
- + ((given & 0x0200) >> 3));
- info->print_address_func (address, info);
- }
- break;
-
- case 's':
- /* Right shift immediate -- bits 6..10; 1-31 print
- as themselves, 0 prints as 32. */
- {
- long imm = (given & 0x07c0) >> 6;
- if (imm == 0)
- imm = 32;
- func (stream, "#%ld", imm);
- }
- break;
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- {
- int bitstart = *c++ - '0';
- int bitend = 0;
-
- while (*c >= '0' && *c <= '9')
- bitstart = (bitstart * 10) + *c++ - '0';
-
- switch (*c)
- {
- case '-':
- {
- long reg;
-
- c++;
- while (*c >= '0' && *c <= '9')
- bitend = (bitend * 10) + *c++ - '0';
- if (!bitend)
- abort ();
- reg = given >> bitstart;
- reg &= (2 << (bitend - bitstart)) - 1;
- switch (*c)
- {
- case 'r':
- func (stream, "%s", arm_regnames[reg]);
- break;
-
- case 'd':
- func (stream, "%ld", reg);
- break;
-
- case 'H':
- func (stream, "%ld", reg << 1);
- break;
-
- case 'W':
- func (stream, "%ld", reg << 2);
- break;
-
- case 'a':
- /* PC-relative address -- the bottom two
- bits of the address are dropped
- before the calculation. */
- info->print_address_func
- (((pc + 4) & ~3) + (reg << 2), info);
- break;
-
- case 'x':
- func (stream, "0x%04lx", reg);
- break;
-
- case 'B':
- reg = ((reg ^ (1 << bitend)) - (1 << bitend));
- info->print_address_func (reg * 2 + pc + 4, info);
- break;
-
- case 'c':
- func (stream, "%s", arm_conditional [reg]);
- break;
-
- default:
- abort ();
- }
- }
- break;
-
- case '\'':
- c++;
- if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c);
- break;
-
- case '?':
- ++c;
- if ((given & (1 << bitstart)) != 0)
- func (stream, "%c", *c++);
- else
- func (stream, "%c", *++c);
- break;
-
- default:
- abort ();
- }
- }
- break;
-
- default:
- abort ();
- }
- }
- return;
- }
-
- /* No match. */
- abort ();
-}
-
-/* Return the name of an V7M special register. */
-static const char *
-psr_name (int regno)
-{
- switch (regno)
- {
- case 0: return "APSR";
- case 1: return "IAPSR";
- case 2: return "EAPSR";
- case 3: return "PSR";
- case 5: return "IPSR";
- case 6: return "EPSR";
- case 7: return "IEPSR";
- case 8: return "MSP";
- case 9: return "PSP";
- case 16: return "PRIMASK";
- case 17: return "BASEPRI";
- case 18: return "BASEPRI_MASK";
- case 19: return "FAULTMASK";
- case 20: return "CONTROL";
- default: return "<unknown>";
- }
-}
-
-/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
-
-static void
-print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
-{
- const struct opcode32 *insn;
- void *stream = info->stream;
- fprintf_function func = info->fprintf_func;
-
- if (print_insn_coprocessor (pc, info, given, true))
- return;
-
- if (print_insn_neon (info, given, true))
- return;
-
- for (insn = thumb32_opcodes; insn->assembler; insn++)
- if ((given & insn->mask) == insn->value)
- {
- const char *c = insn->assembler;
- for (; *c; c++)
- {
- if (*c != '%')
- {
- func (stream, "%c", *c);
- continue;
- }
-
- switch (*++c)
- {
- case '%':
- func (stream, "%%");
- break;
-
- case 'c':
- if (ifthen_state)
- func (stream, "%s", arm_conditional[IFTHEN_COND]);
- break;
-
- case 'x':
- if (ifthen_next_state)
- func (stream, "\t; unpredictable branch in IT block\n");
- break;
-
- case 'X':
- if (ifthen_state)
- func (stream, "\t; unpredictable <IT:%s>",
- arm_conditional[IFTHEN_COND]);
- break;
-
- case 'I':
- {
- unsigned int imm12 = 0;
- imm12 |= (given & 0x000000ffu);
- imm12 |= (given & 0x00007000u) >> 4;
- imm12 |= (given & 0x04000000u) >> 15;
- func (stream, "#%u\t; 0x%x", imm12, imm12);
- }
- break;
-
- case 'M':
- {
- unsigned int bits = 0, imm, imm8, mod;
- bits |= (given & 0x000000ffu);
- bits |= (given & 0x00007000u) >> 4;
- bits |= (given & 0x04000000u) >> 15;
- imm8 = (bits & 0x0ff);
- mod = (bits & 0xf00) >> 8;
- switch (mod)
- {
- case 0: imm = imm8; break;
- case 1: imm = ((imm8<<16) | imm8); break;
- case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
- case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
- default:
- mod = (bits & 0xf80) >> 7;
- imm8 = (bits & 0x07f) | 0x80;
- imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
- }
- func (stream, "#%u\t; 0x%x", imm, imm);
- }
- break;
-
- case 'J':
- {
- unsigned int imm = 0;
- imm |= (given & 0x000000ffu);
- imm |= (given & 0x00007000u) >> 4;
- imm |= (given & 0x04000000u) >> 15;
- imm |= (given & 0x000f0000u) >> 4;
- func (stream, "#%u\t; 0x%x", imm, imm);
- }
- break;
-
- case 'K':
- {
- unsigned int imm = 0;
- imm |= (given & 0x000f0000u) >> 16;
- imm |= (given & 0x00000ff0u) >> 0;
- imm |= (given & 0x0000000fu) << 12;
- func (stream, "#%u\t; 0x%x", imm, imm);
- }
- break;
-
- case 'S':
- {
- unsigned int reg = (given & 0x0000000fu);
- unsigned int stp = (given & 0x00000030u) >> 4;
- unsigned int imm = 0;
- imm |= (given & 0x000000c0u) >> 6;
- imm |= (given & 0x00007000u) >> 10;
-
- func (stream, "%s", arm_regnames[reg]);
- switch (stp)
- {
- case 0:
- if (imm > 0)
- func (stream, ", lsl #%u", imm);
- break;
-
- case 1:
- if (imm == 0)
- imm = 32;
- func (stream, ", lsr #%u", imm);
- break;
-
- case 2:
- if (imm == 0)
- imm = 32;
- func (stream, ", asr #%u", imm);
- break;
-
- case 3:
- if (imm == 0)
- func (stream, ", rrx");
- else
- func (stream, ", ror #%u", imm);
- }
- }
- break;
-
- case 'a':
- {
- unsigned int Rn = (given & 0x000f0000) >> 16;
- unsigned int U = (given & 0x00800000) >> 23;
- unsigned int op = (given & 0x00000f00) >> 8;
- unsigned int i12 = (given & 0x00000fff);
- unsigned int i8 = (given & 0x000000ff);
- bfd_boolean writeback = false, postind = false;
- int offset = 0;
-
- func (stream, "[%s", arm_regnames[Rn]);
- if (U) /* 12-bit positive immediate offset */
- offset = i12;
- else if (Rn == 15) /* 12-bit negative immediate offset */
- offset = -(int)i12;
- else if (op == 0x0) /* shifted register offset */
- {
- unsigned int Rm = (i8 & 0x0f);
- unsigned int sh = (i8 & 0x30) >> 4;
- func (stream, ", %s", arm_regnames[Rm]);
- if (sh)
- func (stream, ", lsl #%u", sh);
- func (stream, "]");
- break;
- }
- else switch (op)
- {
- case 0xE: /* 8-bit positive immediate offset */
- offset = i8;
- break;
-
- case 0xC: /* 8-bit negative immediate offset */
- offset = -i8;
- break;
-
- case 0xF: /* 8-bit + preindex with wb */
- offset = i8;
- writeback = true;
- break;
-
- case 0xD: /* 8-bit - preindex with wb */
- offset = -i8;
- writeback = true;
- break;
-
- case 0xB: /* 8-bit + postindex */
- offset = i8;
- postind = true;
- break;
-
- case 0x9: /* 8-bit - postindex */
- offset = -i8;
- postind = true;
- break;
-
- default:
- func (stream, ", <undefined>]");
- goto skip;
- }
-
- if (postind)
- func (stream, "], #%d", offset);
- else
- {
- if (offset)
- func (stream, ", #%d", offset);
- func (stream, writeback ? "]!" : "]");
- }
-
- if (Rn == 15)
- {
- func (stream, "\t; ");
- info->print_address_func (((pc + 4) & ~3) + offset, info);
- }
- }
- skip:
- break;
-
- case 'A':
- {
- unsigned int P = (given & 0x01000000) >> 24;
- unsigned int U = (given & 0x00800000) >> 23;
- unsigned int W = (given & 0x00400000) >> 21;
- unsigned int Rn = (given & 0x000f0000) >> 16;
- unsigned int off = (given & 0x000000ff);
-
- func (stream, "[%s", arm_regnames[Rn]);
- if (P)
- {
- if (off || !U)
- func (stream, ", #%c%u", U ? '+' : '-', off * 4);
- func (stream, "]");
- if (W)
- func (stream, "!");
- }
- else
- {
- func (stream, "], ");
- if (W)
- func (stream, "#%c%u", U ? '+' : '-', off * 4);
- else
- func (stream, "{%u}", off);
- }
- }
- break;
-
- case 'w':
- {
- unsigned int Sbit = (given & 0x01000000) >> 24;
- unsigned int type = (given & 0x00600000) >> 21;
- switch (type)
- {
- case 0: func (stream, Sbit ? "sb" : "b"); break;
- case 1: func (stream, Sbit ? "sh" : "h"); break;
- case 2:
- if (Sbit)
- func (stream, "??");
- break;
- case 3:
- func (stream, "??");
- break;
- }
- }
- break;
-
- case 'm':
- {
- int started = 0;
- int reg;
-
- func (stream, "{");
- for (reg = 0; reg < 16; reg++)
- if ((given & (1 << reg)) != 0)
- {
- if (started)
- func (stream, ", ");
- started = 1;
- func (stream, "%s", arm_regnames[reg]);
- }
- func (stream, "}");
- }
- break;
-
- case 'E':
- {
- unsigned int msb = (given & 0x0000001f);
- unsigned int lsb = 0;
- lsb |= (given & 0x000000c0u) >> 6;
- lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, msb - lsb + 1);
- }
- break;
-
- case 'F':
- {
- unsigned int width = (given & 0x0000001f) + 1;
- unsigned int lsb = 0;
- lsb |= (given & 0x000000c0u) >> 6;
- lsb |= (given & 0x00007000u) >> 10;
- func (stream, "#%u, #%u", lsb, width);
- }
- break;
-
- case 'b':
- {
- unsigned int S = (given & 0x04000000u) >> 26;
- unsigned int J1 = (given & 0x00002000u) >> 13;
- unsigned int J2 = (given & 0x00000800u) >> 11;
- int offset = 0;
-
- offset |= !S << 20;
- offset |= J2 << 19;
- offset |= J1 << 18;
- offset |= (given & 0x003f0000) >> 4;
- offset |= (given & 0x000007ff) << 1;
- offset -= (1 << 20);
-
- info->print_address_func (pc + 4 + offset, info);
- }
- break;
-
- case 'B':
- {
- unsigned int S = (given & 0x04000000u) >> 26;
- unsigned int I1 = (given & 0x00002000u) >> 13;
- unsigned int I2 = (given & 0x00000800u) >> 11;
- int offset = 0;
-
- offset |= !S << 24;
- offset |= !(I1 ^ S) << 23;
- offset |= !(I2 ^ S) << 22;
- offset |= (given & 0x03ff0000u) >> 4;
- offset |= (given & 0x000007ffu) << 1;
- offset -= (1 << 24);
- offset += pc + 4;
-
- /* BLX target addresses are always word aligned. */
- if ((given & 0x00001000u) == 0)
- offset &= ~2u;
-
- info->print_address_func (offset, info);
- }
- break;
-
- case 's':
- {
- unsigned int shift = 0;
- shift |= (given & 0x000000c0u) >> 6;
- shift |= (given & 0x00007000u) >> 10;
- if (given & 0x00200000u)
- func (stream, ", asr #%u", shift);
- else if (shift)
- func (stream, ", lsl #%u", shift);
- /* else print nothing - lsl #0 */
- }
- break;
-
- case 'R':
- {
- unsigned int rot = (given & 0x00000030) >> 4;
- if (rot)
- func (stream, ", ror #%u", rot * 8);
- }
- break;
-
- case 'U':
- switch (given & 0xf)
- {
- case 0xf: func(stream, "sy"); break;
- case 0x7: func(stream, "un"); break;
- case 0xe: func(stream, "st"); break;
- case 0x6: func(stream, "unst"); break;
- default:
- func(stream, "#%d", (int)given & 0xf);
- break;
- }
- break;
-
- case 'C':
- if ((given & 0xff) == 0)
- {
- func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
- if (given & 0x800)
- func (stream, "f");
- if (given & 0x400)
- func (stream, "s");
- if (given & 0x200)
- func (stream, "x");
- if (given & 0x100)
- func (stream, "c");
- }
- else
- {
- func (stream, "%s", psr_name (given & 0xff));
- }
- break;
-
- case 'D':
- if ((given & 0xff) == 0)
- func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
- else
- func (stream, "%s", psr_name (given & 0xff));
- break;
-
- case '0': case '1': case '2': case '3': case '4':
- case '5': case '6': case '7': case '8': case '9':
- {
- int width;
- unsigned long val;
-
- c = arm_decode_bitfield (c, given, &val, &width);
-
- switch (*c)
- {
- case 'd': func (stream, "%lu", val); break;
- case 'W': func (stream, "%lu", val * 4); break;
- case 'r': func (stream, "%s", arm_regnames[val]); break;
-
- case 'c':
- func (stream, "%s", arm_conditional[val]);
- break;
-
- case '\'':
- c++;
- if (val == ((1ul << width) - 1))
- func (stream, "%c", *c);
- break;
-
- case '`':
- c++;
- if (val == 0)
- func (stream, "%c", *c);
- break;
-
- case '?':
- func (stream, "%c", c[(1 << width) - (int)val]);
- c += 1 << width;
- break;
-
- default:
- abort ();
- }
- }
- break;
-
- default:
- abort ();
- }
- }
- return;
- }
-
- /* No match. */
- abort ();
-}
-
-/* Print data bytes on INFO->STREAM. */
-
-static void
-print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
- long given)
-{
- switch (info->bytes_per_chunk)
- {
- case 1:
- info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
- break;
- case 2:
- info->fprintf_func (info->stream, ".short\t0x%04lx", given);
- break;
- case 4:
- info->fprintf_func (info->stream, ".word\t0x%08lx", given);
- break;
- default:
- abort ();
- }
-}
-
-/* Search back through the insn stream to determine if this instruction is
- conditionally executed. */
-static void
-find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
- bfd_boolean little)
-{
- unsigned char b[2];
- unsigned int insn;
- int status;
- /* COUNT is twice the number of instructions seen. It will be odd if we
- just crossed an instruction boundary. */
- int count;
- int it_count;
- unsigned int seen_it;
- bfd_vma addr;
-
- ifthen_address = pc;
- ifthen_state = 0;
-
- addr = pc;
- count = 1;
- it_count = 0;
- seen_it = 0;
- /* Scan backwards looking for IT instructions, keeping track of where
- instruction boundaries are. We don't know if something is actually an
- IT instruction until we find a definite instruction boundary. */
- for (;;)
- {
- if (addr == 0 || info->symbol_at_address_func(addr, info))
- {
- /* A symbol must be on an instruction boundary, and will not
- be within an IT block. */
- if (seen_it && (count & 1))
- break;
-
- return;
- }
- addr -= 2;
- status = arm_read_memory (addr, (bfd_byte *)b, 2, info);
- if (status)
- return;
-
- if (little)
- insn = (b[0]) | (b[1] << 8);
- else
- insn = (b[1]) | (b[0] << 8);
- if (seen_it)
- {
- if ((insn & 0xf800) < 0xe800)
- {
- /* Addr + 2 is an instruction boundary. See if this matches
- the expected boundary based on the position of the last
- IT candidate. */
- if (count & 1)
- break;
- seen_it = 0;
- }
- }
- if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
- {
- /* This could be an IT instruction. */
- seen_it = insn;
- it_count = count >> 1;
- }
- if ((insn & 0xf800) >= 0xe800)
- count++;
- else
- count = (count + 2) | 1;
- /* IT blocks contain at most 4 instructions. */
- if (count >= 8 && !seen_it)
- return;
- }
- /* We found an IT instruction. */
- ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
- if ((ifthen_state & 0xf) == 0)
- ifthen_state = 0;
-}
-
-/* NOTE: There are no checks in these routines that
- the relevant number of data bytes exist. */
-
-int
-print_insn_arm (bfd_vma pc, struct disassemble_info *info)
-{
- unsigned char b[4];
- long given;
- int status;
- int is_thumb = false;
- int is_data = false;
- unsigned int size = 4;
- void (*printer) (bfd_vma, struct disassemble_info *, long);
- int little;
-
- little = (info->endian == BFD_ENDIAN_LITTLE);
- is_thumb |= (pc & 1);
- pc &= ~(bfd_vma)1;
-
- if (force_thumb)
- is_thumb = true;
-
- info->bytes_per_line = 4;
-
- if (is_data)
- {
- int i;
-
- /* size was already set above. */
- info->bytes_per_chunk = size;
- printer = print_insn_data;
-
- status = arm_read_memory (pc, (bfd_byte *)b, size, info);
- given = 0;
- if (little)
- for (i = size - 1; i >= 0; i--)
- given = b[i] | (given << 8);
- else
- for (i = 0; i < (int) size; i++)
- given = b[i] | (given << 8);
- }
- else if (!is_thumb)
- {
- /* In ARM mode endianness is a straightforward issue: the instruction
- is four bytes long and is either ordered 0123 or 3210. */
- printer = print_insn_arm_internal;
- info->bytes_per_chunk = 4;
- size = 4;
-
- status = arm_read_memory (pc, (bfd_byte *)b, 4, info);
- if (little)
- given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned)b[3] << 24);
- else
- given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned)b[0] << 24);
- }
- else
- {
- /* In Thumb mode we have the additional wrinkle of two
- instruction lengths. Fortunately, the bits that determine
- the length of the current instruction are always to be found
- in the first two bytes. */
- printer = print_insn_thumb16;
- info->bytes_per_chunk = 2;
- size = 2;
-
- status = arm_read_memory (pc, (bfd_byte *)b, 2, info);
- if (little)
- given = (b[0]) | (b[1] << 8);
- else
- given = (b[1]) | (b[0] << 8);
-
- if (!status)
- {
- /* These bit patterns signal a four-byte Thumb
- instruction. */
- if ((given & 0xF800) == 0xF800
- || (given & 0xF800) == 0xF000
- || (given & 0xF800) == 0xE800)
- {
- status = arm_read_memory (pc + 2, (bfd_byte *)b, 2, info);
- if (little)
- given = (b[0]) | (b[1] << 8) | (given << 16);
- else
- given = (b[1]) | (b[0] << 8) | (given << 16);
-
- printer = print_insn_thumb32;
- size = 4;
- }
- }
-
- if (ifthen_address != pc)
- find_ifthen_state(pc, info, little);
-
- if (ifthen_state)
- {
- if ((ifthen_state & 0xf) == 0x8)
- ifthen_next_state = 0;
- else
- ifthen_next_state = (ifthen_state & 0xe0)
- | ((ifthen_state & 0xf) << 1);
- }
- }
-
- if (status)
- {
- info->memory_error_func (status, pc, info);
- return -1;
- }
- if (info->flags & INSN_HAS_RELOC)
- /* If the instruction has a reloc associated with it, then
- the offset field in the instruction will actually be the
- addend for the reloc. (We are using REL type relocs).
- In such cases, we can ignore the pc when computing
- addresses, since the addend is not currently pc-relative. */
- pc = 0;
-
- /* We include the hexdump of the instruction. The format here
- matches that used by objdump and the ARM ARM (in particular,
- 32 bit Thumb instructions are displayed as pairs of halfwords,
- not as a single word.) */
- if (is_thumb)
- {
- if (size == 2)
- {
- info->fprintf_func(info->stream, "%04lx ",
- ((unsigned long)given) & 0xffff);
- }
- else
- {
- info->fprintf_func(info->stream, "%04lx %04lx ",
- (((unsigned long)given) >> 16) & 0xffff,
- ((unsigned long)given) & 0xffff);
- }
- }
- else
- {
- info->fprintf_func(info->stream, "%08lx ",
- ((unsigned long)given) & 0xffffffff);
- }
-
- printer (pc, info, given);
-
- if (is_thumb)
- {
- ifthen_state = ifthen_next_state;
- ifthen_address += size;
- }
- return size;
-}
diff --git a/disas/i386.c b/disas/i386.c
deleted file mode 100644
index 06c835236e..0000000000
--- a/disas/i386.c
+++ /dev/null
@@ -1,6771 +0,0 @@
-/* opcodes/i386-dis.c r1.126 */
-/* Print i386 instructions for GDB, the GNU debugger.
- Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
-
- This file is part of GDB.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
- July 1988
- modified by John Hassey (hassey@dg-rtp.dg.com)
- x86-64 support added by Jan Hubicka (jh@suse.cz)
- VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
-
-/* The main tables describing the instructions is essentially a copy
- of the "Opcode Map" chapter (Appendix A) of the Intel 80386
- Programmers Manual. Usually, there is a capital letter, followed
- by a small letter. The capital letter tell the addressing mode,
- and the small letter tells about the operand size. Refer to
- the Intel manual for details. */
-
-#include "qemu/osdep.h"
-#include "disas/dis-asm.h"
-#include "qemu/cutils.h"
-
-/* include/opcode/i386.h r1.78 */
-
-/* opcode/i386.h -- Intel 80386 opcode macros
- Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
- Free Software Foundation, Inc.
-
- This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, see <http://www.gnu.org/licenses/>. */
-
-/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
- ix86 Unix assemblers, generate floating point instructions with
- reversed source and destination registers in certain cases.
- Unfortunately, gcc and possibly many other programs use this
- reversed syntax, so we're stuck with it.
-
- eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
- `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
- the expected st(3) = st(3) - st
-
- This happens with all the non-commutative arithmetic floating point
- operations with two register operands, where the source register is
- %st, and destination register is %st(i).
-
- The affected opcode map is dceX, dcfX, deeX, defX. */
-
-#ifndef SYSV386_COMPAT
-/* Set non-zero for broken, compatible instructions. Set to zero for
- non-broken opcodes at your peril. gcc generates SystemV/386
- compatible instructions. */
-#define SYSV386_COMPAT 1
-#endif
-#ifndef OLDGCC_COMPAT
-/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
- generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
- reversed. */
-#define OLDGCC_COMPAT SYSV386_COMPAT
-#endif
-
-#define MOV_AX_DISP32 0xa0
-#define POP_SEG_SHORT 0x07
-#define JUMP_PC_RELATIVE 0xeb
-#define INT_OPCODE 0xcd
-#define INT3_OPCODE 0xcc
-/* The opcode for the fwait instruction, which disassembler treats as a
- prefix when it can. */
-#define FWAIT_OPCODE 0x9b
-#define ADDR_PREFIX_OPCODE 0x67
-#define DATA_PREFIX_OPCODE 0x66
-#define LOCK_PREFIX_OPCODE 0xf0
-#define CS_PREFIX_OPCODE 0x2e
-#define DS_PREFIX_OPCODE 0x3e
-#define ES_PREFIX_OPCODE 0x26
-#define FS_PREFIX_OPCODE 0x64
-#define GS_PREFIX_OPCODE 0x65
-#define SS_PREFIX_OPCODE 0x36
-#define REPNE_PREFIX_OPCODE 0xf2
-#define REPE_PREFIX_OPCODE 0xf3
-
-#define TWO_BYTE_OPCODE_ESCAPE 0x0f
-#define NOP_OPCODE (char) 0x90
-
-/* register numbers */
-#define EBP_REG_NUM 5
-#define ESP_REG_NUM 4
-
-/* modrm_byte.regmem for twobyte escape */
-#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
-/* index_base_byte.index for no index register addressing */
-#define NO_INDEX_REGISTER ESP_REG_NUM
-/* index_base_byte.base for no base register addressing */
-#define NO_BASE_REGISTER EBP_REG_NUM
-#define NO_BASE_REGISTER_16 6
-
-/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
-#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
-#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
-
-/* x86-64 extension prefix. */
-#define REX_OPCODE 0x40
-
-/* Indicates 64 bit operand size. */
-#define REX_W 8
-/* High extension to reg field of modrm byte. */
-#define REX_R 4
-/* High extension to SIB index field. */
-#define REX_X 2
-/* High extension to base field of modrm or SIB, or reg field of opcode. */
-#define REX_B 1
-
-/* max operands per insn */
-#define MAX_OPERANDS 4
-
-/* max immediates per insn (lcall, ljmp, insertq, extrq) */
-#define MAX_IMMEDIATE_OPERANDS 2
-
-/* max memory refs per insn (string ops) */
-#define MAX_MEMORY_OPERANDS 2
-
-/* max size of insn mnemonics. */
-#define MAX_MNEM_SIZE 16
-
-/* max size of register name in insn mnemonics. */
-#define MAX_REG_NAME_SIZE 8
-
-/* opcodes/i386-dis.c r1.126 */
-
-static int fetch_data2(struct disassemble_info *, bfd_byte *);
-static int fetch_data(struct disassemble_info *, bfd_byte *);
-static void ckprefix (void);
-static const char *prefix_name (int, int);
-static int print_insn (bfd_vma, disassemble_info *);
-static void dofloat (int);
-static void OP_ST (int, int);
-static void OP_STi (int, int);
-static int putop (const char *, int);
-static void oappend (const char *);
-static void append_seg (void);
-static void OP_indirE (int, int);
-static void print_operand_value (char *buf, size_t bufsize, int hex, bfd_vma disp);
-static void print_displacement (char *, bfd_vma);
-static void OP_E (int, int);
-static void OP_G (int, int);
-static void OP_vvvv (int, int);
-static bfd_vma get64 (void);
-static bfd_signed_vma get32 (void);
-static bfd_signed_vma get32s (void);
-static int get16 (void);
-static void set_op (bfd_vma, int);
-static void OP_REG (int, int);
-static void OP_IMREG (int, int);
-static void OP_I (int, int);
-static void OP_I64 (int, int);
-static void OP_sI (int, int);
-static void OP_J (int, int);
-static void OP_SEG (int, int);
-static void OP_DIR (int, int);
-static void OP_OFF (int, int);
-static void OP_OFF64 (int, int);
-static void ptr_reg (int, int);
-static void OP_ESreg (int, int);
-static void OP_DSreg (int, int);
-static void OP_C (int, int);
-static void OP_D (int, int);
-static void OP_T (int, int);
-static void OP_R (int, int);
-static void OP_MMX (int, int);
-static void OP_XMM (int, int);
-static void OP_EM (int, int);
-static void OP_EX (int, int);
-static void OP_EMC (int,int);
-static void OP_MXC (int,int);
-static void OP_MS (int, int);
-static void OP_XS (int, int);
-static void OP_M (int, int);
-static void OP_VMX (int, int);
-static void OP_0fae (int, int);
-static void OP_0f07 (int, int);
-static void NOP_Fixup1 (int, int);
-static void NOP_Fixup2 (int, int);
-static void OP_3DNowSuffix (int, int);
-static void OP_SIMD_Suffix (int, int);
-static void SIMD_Fixup (int, int);
-static void PNI_Fixup (int, int);
-static void SVME_Fixup (int, int);
-static void INVLPG_Fixup (int, int);
-static void BadOp (void);
-static void VMX_Fixup (int, int);
-static void REP_Fixup (int, int);
-static void CMPXCHG8B_Fixup (int, int);
-static void XMM_Fixup (int, int);
-static void CRC32_Fixup (int, int);
-
-struct dis_private {
- /* Points to first byte not fetched. */
- bfd_byte *max_fetched;
- bfd_byte the_buffer[MAX_MNEM_SIZE];
- bfd_vma insn_start;
- int orig_sizeflag;
- sigjmp_buf bailout;
-};
-
-enum address_mode
-{
- mode_16bit,
- mode_32bit,
- mode_64bit
-};
-
-static enum address_mode address_mode;
-
-/* Flags for the prefixes for the current instruction. See below. */
-static int prefixes;
-
-/* REX prefix the current instruction. See below. */
-static int rex;
-/* Bits of REX we've already used. */
-static int rex_used;
-/* Mark parts used in the REX prefix. When we are testing for
- empty prefix (for 8bit register REX extension), just mask it
- out. Otherwise test for REX bit is excuse for existence of REX
- only in case value is nonzero. */
-#define USED_REX(value) \
- { \
- if (value) \
- { \
- if ((rex & value)) \
- rex_used |= (value) | REX_OPCODE; \
- } \
- else \
- rex_used |= REX_OPCODE; \
- }
-
-/* Flags for prefixes which we somehow handled when printing the
- current instruction. */
-static int used_prefixes;
-
-/* The VEX.vvvv register, unencoded. */
-static int vex_reg;
-
-/* Flags stored in PREFIXES. */
-#define PREFIX_REPZ 1
-#define PREFIX_REPNZ 2
-#define PREFIX_LOCK 4
-#define PREFIX_CS 8
-#define PREFIX_SS 0x10
-#define PREFIX_DS 0x20
-#define PREFIX_ES 0x40
-#define PREFIX_FS 0x80
-#define PREFIX_GS 0x100
-#define PREFIX_DATA 0x200
-#define PREFIX_ADDR 0x400
-#define PREFIX_FWAIT 0x800
-
-#define PREFIX_VEX_0F 0x1000
-#define PREFIX_VEX_0F38 0x2000
-#define PREFIX_VEX_0F3A 0x4000
-
-/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
- to ADDR (exclusive) are valid. Returns 1 for success, longjmps
- on error. */
-static int
-fetch_data2(struct disassemble_info *info, bfd_byte *addr)
-{
- int status;
- struct dis_private *priv = (struct dis_private *) info->private_data;
- bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
-
- if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
- status = (*info->read_memory_func) (start,
- priv->max_fetched,
- addr - priv->max_fetched,
- info);
- else
- status = -1;
- if (status != 0)
- {
- /* If we did manage to read at least one byte, then
- print_insn_i386 will do something sensible. Otherwise, print
- an error. We do that here because this is where we know
- STATUS. */
- if (priv->max_fetched == priv->the_buffer)
- (*info->memory_error_func) (status, start, info);
- siglongjmp(priv->bailout, 1);
- }
- else
- priv->max_fetched = addr;
- return 1;
-}
-
-static int
-fetch_data(struct disassemble_info *info, bfd_byte *addr)
-{
- if (addr <= ((struct dis_private *) (info->private_data))->max_fetched) {
- return 1;
- } else {
- return fetch_data2(info, addr);
- }
-}
-
-
-#define XX { NULL, 0 }
-
-#define Bv { OP_vvvv, v_mode }
-#define Eb { OP_E, b_mode }
-#define Ev { OP_E, v_mode }
-#define Ed { OP_E, d_mode }
-#define Edq { OP_E, dq_mode }
-#define Edqw { OP_E, dqw_mode }
-#define Edqb { OP_E, dqb_mode }
-#define Edqd { OP_E, dqd_mode }
-#define indirEv { OP_indirE, stack_v_mode }
-#define indirEp { OP_indirE, f_mode }
-#define stackEv { OP_E, stack_v_mode }
-#define Em { OP_E, m_mode }
-#define Ew { OP_E, w_mode }
-#define M { OP_M, 0 } /* lea, lgdt, etc. */
-#define Ma { OP_M, v_mode }
-#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
-#define Mq { OP_M, q_mode }
-#define Gb { OP_G, b_mode }
-#define Gv { OP_G, v_mode }
-#define Gd { OP_G, d_mode }
-#define Gdq { OP_G, dq_mode }
-#define Gm { OP_G, m_mode }
-#define Gw { OP_G, w_mode }
-#define Rd { OP_R, d_mode }
-#define Rm { OP_R, m_mode }
-#define Ib { OP_I, b_mode }
-#define sIb { OP_sI, b_mode } /* sign extended byte */
-#define Iv { OP_I, v_mode }
-#define Iq { OP_I, q_mode }
-#define Iv64 { OP_I64, v_mode }
-#define Iw { OP_I, w_mode }
-#define I1 { OP_I, const_1_mode }
-#define Jb { OP_J, b_mode }
-#define Jv { OP_J, v_mode }
-#define Cm { OP_C, m_mode }
-#define Dm { OP_D, m_mode }
-#define Td { OP_T, d_mode }
-
-#define RMeAX { OP_REG, eAX_reg }
-#define RMeBX { OP_REG, eBX_reg }
-#define RMeCX { OP_REG, eCX_reg }
-#define RMeDX { OP_REG, eDX_reg }
-#define RMeSP { OP_REG, eSP_reg }
-#define RMeBP { OP_REG, eBP_reg }
-#define RMeSI { OP_REG, eSI_reg }
-#define RMeDI { OP_REG, eDI_reg }
-#define RMrAX { OP_REG, rAX_reg }
-#define RMrBX { OP_REG, rBX_reg }
-#define RMrCX { OP_REG, rCX_reg }
-#define RMrDX { OP_REG, rDX_reg }
-#define RMrSP { OP_REG, rSP_reg }
-#define RMrBP { OP_REG, rBP_reg }
-#define RMrSI { OP_REG, rSI_reg }
-#define RMrDI { OP_REG, rDI_reg }
-#define RMAL { OP_REG, al_reg }
-#define RMAL { OP_REG, al_reg }
-#define RMCL { OP_REG, cl_reg }
-#define RMDL { OP_REG, dl_reg }
-#define RMBL { OP_REG, bl_reg }
-#define RMAH { OP_REG, ah_reg }
-#define RMCH { OP_REG, ch_reg }
-#define RMDH { OP_REG, dh_reg }
-#define RMBH { OP_REG, bh_reg }
-#define RMAX { OP_REG, ax_reg }
-#define RMDX { OP_REG, dx_reg }
-
-#define eAX { OP_IMREG, eAX_reg }
-#define eBX { OP_IMREG, eBX_reg }
-#define eCX { OP_IMREG, eCX_reg }
-#define eDX { OP_IMREG, eDX_reg }
-#define eSP { OP_IMREG, eSP_reg }
-#define eBP { OP_IMREG, eBP_reg }
-#define eSI { OP_IMREG, eSI_reg }
-#define eDI { OP_IMREG, eDI_reg }
-#define AL { OP_IMREG, al_reg }
-#define CL { OP_IMREG, cl_reg }
-#define DL { OP_IMREG, dl_reg }
-#define BL { OP_IMREG, bl_reg }
-#define AH { OP_IMREG, ah_reg }
-#define CH { OP_IMREG, ch_reg }
-#define DH { OP_IMREG, dh_reg }
-#define BH { OP_IMREG, bh_reg }
-#define AX { OP_IMREG, ax_reg }
-#define DX { OP_IMREG, dx_reg }
-#define zAX { OP_IMREG, z_mode_ax_reg }
-#define indirDX { OP_IMREG, indir_dx_reg }
-
-#define Sw { OP_SEG, w_mode }
-#define Sv { OP_SEG, v_mode }
-#define Ap { OP_DIR, 0 }
-#define Ob { OP_OFF64, b_mode }
-#define Ov { OP_OFF64, v_mode }
-#define Xb { OP_DSreg, eSI_reg }
-#define Xv { OP_DSreg, eSI_reg }
-#define Xz { OP_DSreg, eSI_reg }
-#define Yb { OP_ESreg, eDI_reg }
-#define Yv { OP_ESreg, eDI_reg }
-#define DSBX { OP_DSreg, eBX_reg }
-
-#define es { OP_REG, es_reg }
-#define ss { OP_REG, ss_reg }
-#define cs { OP_REG, cs_reg }
-#define ds { OP_REG, ds_reg }
-#define fs { OP_REG, fs_reg }
-#define gs { OP_REG, gs_reg }
-
-#define MX { OP_MMX, 0 }
-#define XM { OP_XMM, 0 }
-#define EM { OP_EM, v_mode }
-#define EMd { OP_EM, d_mode }
-#define EMq { OP_EM, q_mode }
-#define EXd { OP_EX, d_mode }
-#define EXq { OP_EX, q_mode }
-#define EXx { OP_EX, x_mode }
-#define MS { OP_MS, v_mode }
-#define XS { OP_XS, v_mode }
-#define EMC { OP_EMC, v_mode }
-#define MXC { OP_MXC, 0 }
-#define VM { OP_VMX, q_mode }
-#define OPSUF { OP_3DNowSuffix, 0 }
-#define OPSIMD { OP_SIMD_Suffix, 0 }
-#define XMM0 { XMM_Fixup, 0 }
-
-/* Used handle "rep" prefix for string instructions. */
-#define Xbr { REP_Fixup, eSI_reg }
-#define Xvr { REP_Fixup, eSI_reg }
-#define Ybr { REP_Fixup, eDI_reg }
-#define Yvr { REP_Fixup, eDI_reg }
-#define Yzr { REP_Fixup, eDI_reg }
-#define indirDXr { REP_Fixup, indir_dx_reg }
-#define ALr { REP_Fixup, al_reg }
-#define eAXr { REP_Fixup, eAX_reg }
-
-#define cond_jump_flag { NULL, cond_jump_mode }
-#define loop_jcxz_flag { NULL, loop_jcxz_mode }
-
-/* bits in sizeflag */
-#define SUFFIX_ALWAYS 4
-#define AFLAG 2
-#define DFLAG 1
-
-#define b_mode 1 /* byte operand */
-#define v_mode 2 /* operand size depends on prefixes */
-#define w_mode 3 /* word operand */
-#define d_mode 4 /* double word operand */
-#define q_mode 5 /* quad word operand */
-#define t_mode 6 /* ten-byte operand */
-#define x_mode 7 /* 16-byte XMM operand */
-#define m_mode 8 /* d_mode in 32bit, q_mode in 64bit mode. */
-#define cond_jump_mode 9
-#define loop_jcxz_mode 10
-#define dq_mode 11 /* operand size depends on REX prefixes. */
-#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
-#define f_mode 13 /* 4- or 6-byte pointer operand */
-#define const_1_mode 14
-#define stack_v_mode 15 /* v_mode for stack-related opcodes. */
-#define z_mode 16 /* non-quad operand size depends on prefixes */
-#define o_mode 17 /* 16-byte operand */
-#define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */
-#define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */
-
-#define es_reg 100
-#define cs_reg 101
-#define ss_reg 102
-#define ds_reg 103
-#define fs_reg 104
-#define gs_reg 105
-
-#define eAX_reg 108
-#define eCX_reg 109
-#define eDX_reg 110
-#define eBX_reg 111
-#define eSP_reg 112
-#define eBP_reg 113
-#define eSI_reg 114
-#define eDI_reg 115
-
-#define al_reg 116
-#define cl_reg 117
-#define dl_reg 118
-#define bl_reg 119
-#define ah_reg 120
-#define ch_reg 121
-#define dh_reg 122
-#define bh_reg 123
-
-#define ax_reg 124
-#define cx_reg 125
-#define dx_reg 126
-#define bx_reg 127
-#define sp_reg 128
-#define bp_reg 129
-#define si_reg 130
-#define di_reg 131
-
-#define rAX_reg 132
-#define rCX_reg 133
-#define rDX_reg 134
-#define rBX_reg 135
-#define rSP_reg 136
-#define rBP_reg 137
-#define rSI_reg 138
-#define rDI_reg 139
-
-#define z_mode_ax_reg 149
-#define indir_dx_reg 150
-
-#define FLOATCODE 1
-#define USE_GROUPS 2
-#define USE_PREFIX_USER_TABLE 3
-#define X86_64_SPECIAL 4
-#define IS_3BYTE_OPCODE 5
-
-#define FLOAT NULL, { { NULL, FLOATCODE } }
-
-#define GRP1a NULL, { { NULL, USE_GROUPS }, { NULL, 0 } }
-#define GRP1b NULL, { { NULL, USE_GROUPS }, { NULL, 1 } }
-#define GRP1S NULL, { { NULL, USE_GROUPS }, { NULL, 2 } }
-#define GRP1Ss NULL, { { NULL, USE_GROUPS }, { NULL, 3 } }
-#define GRP2b NULL, { { NULL, USE_GROUPS }, { NULL, 4 } }
-#define GRP2S NULL, { { NULL, USE_GROUPS }, { NULL, 5 } }
-#define GRP2b_one NULL, { { NULL, USE_GROUPS }, { NULL, 6 } }
-#define GRP2S_one NULL, { { NULL, USE_GROUPS }, { NULL, 7 } }
-#define GRP2b_cl NULL, { { NULL, USE_GROUPS }, { NULL, 8 } }
-#define GRP2S_cl NULL, { { NULL, USE_GROUPS }, { NULL, 9 } }
-#define GRP3b NULL, { { NULL, USE_GROUPS }, { NULL, 10 } }
-#define GRP3S NULL, { { NULL, USE_GROUPS }, { NULL, 11 } }
-#define GRP4 NULL, { { NULL, USE_GROUPS }, { NULL, 12 } }
-#define GRP5 NULL, { { NULL, USE_GROUPS }, { NULL, 13 } }
-#define GRP6 NULL, { { NULL, USE_GROUPS }, { NULL, 14 } }
-#define GRP7 NULL, { { NULL, USE_GROUPS }, { NULL, 15 } }
-#define GRP8 NULL, { { NULL, USE_GROUPS }, { NULL, 16 } }
-#define GRP9 NULL, { { NULL, USE_GROUPS }, { NULL, 17 } }
-#define GRP11_C6 NULL, { { NULL, USE_GROUPS }, { NULL, 18 } }
-#define GRP11_C7 NULL, { { NULL, USE_GROUPS }, { NULL, 19 } }
-#define GRP12 NULL, { { NULL, USE_GROUPS }, { NULL, 20 } }
-#define GRP13 NULL, { { NULL, USE_GROUPS }, { NULL, 21 } }
-#define GRP14 NULL, { { NULL, USE_GROUPS }, { NULL, 22 } }
-#define GRP15 NULL, { { NULL, USE_GROUPS }, { NULL, 23 } }
-#define GRP16 NULL, { { NULL, USE_GROUPS }, { NULL, 24 } }
-#define GRPAMD NULL, { { NULL, USE_GROUPS }, { NULL, 25 } }
-#define GRPPADLCK1 NULL, { { NULL, USE_GROUPS }, { NULL, 26 } }
-#define GRPPADLCK2 NULL, { { NULL, USE_GROUPS }, { NULL, 27 } }
-
-#define PREGRP0 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 0 } }
-#define PREGRP1 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 1 } }
-#define PREGRP2 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 2 } }
-#define PREGRP3 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 3 } }
-#define PREGRP4 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 4 } }
-#define PREGRP5 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 5 } }
-#define PREGRP6 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 6 } }
-#define PREGRP7 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 7 } }
-#define PREGRP8 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 8 } }
-#define PREGRP9 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 9 } }
-#define PREGRP10 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 10 } }
-#define PREGRP11 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 11 } }
-#define PREGRP12 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 12 } }
-#define PREGRP13 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 13 } }
-#define PREGRP14 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 14 } }
-#define PREGRP15 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 15 } }
-#define PREGRP16 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 16 } }
-#define PREGRP17 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 17 } }
-#define PREGRP18 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 18 } }
-#define PREGRP19 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 19 } }
-#define PREGRP20 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 20 } }
-#define PREGRP21 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 21 } }
-#define PREGRP22 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 22 } }
-#define PREGRP23 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 23 } }
-#define PREGRP24 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 24 } }
-#define PREGRP25 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 25 } }
-#define PREGRP26 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 26 } }
-#define PREGRP27 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 27 } }
-#define PREGRP28 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 28 } }
-#define PREGRP29 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 29 } }
-#define PREGRP30 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 30 } }
-#define PREGRP31 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 31 } }
-#define PREGRP32 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 32 } }
-#define PREGRP33 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 33 } }
-#define PREGRP34 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 34 } }
-#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } }
-#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } }
-#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } }
-#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } }
-#define PREGRP39 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 39 } }
-#define PREGRP40 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 40 } }
-#define PREGRP41 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 41 } }
-#define PREGRP42 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 42 } }
-#define PREGRP43 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 43 } }
-#define PREGRP44 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 44 } }
-#define PREGRP45 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 45 } }
-#define PREGRP46 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 46 } }
-#define PREGRP47 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 47 } }
-#define PREGRP48 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 48 } }
-#define PREGRP49 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 49 } }
-#define PREGRP50 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 50 } }
-#define PREGRP51 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 51 } }
-#define PREGRP52 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 52 } }
-#define PREGRP53 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 53 } }
-#define PREGRP54 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 54 } }
-#define PREGRP55 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 55 } }
-#define PREGRP56 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 56 } }
-#define PREGRP57 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 57 } }
-#define PREGRP58 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 58 } }
-#define PREGRP59 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 59 } }
-#define PREGRP60 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 60 } }
-#define PREGRP61 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 61 } }
-#define PREGRP62 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 62 } }
-#define PREGRP63 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 63 } }
-#define PREGRP64 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 64 } }
-#define PREGRP65 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 65 } }
-#define PREGRP66 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 66 } }
-#define PREGRP67 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 67 } }
-#define PREGRP68 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 68 } }
-#define PREGRP69 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 69 } }
-#define PREGRP70 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 70 } }
-#define PREGRP71 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 71 } }
-#define PREGRP72 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 72 } }
-#define PREGRP73 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 73 } }
-#define PREGRP74 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 74 } }
-#define PREGRP75 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 75 } }
-#define PREGRP76 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 76 } }
-#define PREGRP77 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 77 } }
-#define PREGRP78 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 78 } }
-#define PREGRP79 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 79 } }
-#define PREGRP80 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 80 } }
-#define PREGRP81 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 81 } }
-#define PREGRP82 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 82 } }
-#define PREGRP83 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 83 } }
-#define PREGRP84 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 84 } }
-#define PREGRP85 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 85 } }
-#define PREGRP86 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 86 } }
-#define PREGRP87 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 87 } }
-#define PREGRP88 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 88 } }
-#define PREGRP89 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 89 } }
-#define PREGRP90 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 90 } }
-#define PREGRP91 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 91 } }
-#define PREGRP92 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 92 } }
-#define PREGRP93 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 93 } }
-#define PREGRP94 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 94 } }
-#define PREGRP95 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 95 } }
-#define PREGRP96 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 96 } }
-#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
-#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
-#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
-#define PREGRP100 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 100 } }
-#define PREGRP101 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 101 } }
-#define PREGRP102 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 102 } }
-#define PREGRP103 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 103 } }
-#define PREGRP104 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 104 } }
-#define PREGRP105 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 105 } }
-#define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } }
-#define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } }
-#define PREGRP108 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 108 } }
-#define PREGRP109 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 109 } }
-
-#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
-#define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } }
-#define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } }
-#define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } }
-
-#define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } }
-#define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } }
-
-typedef void (*op_rtn) (int bytemode, int sizeflag);
-
-struct dis386 {
- const char *name;
- struct
- {
- op_rtn rtn;
- int bytemode;
- } op[MAX_OPERANDS];
-};
-
-/* Upper case letters in the instruction names here are macros.
- 'A' => print 'b' if no register operands or suffix_always is true
- 'B' => print 'b' if suffix_always is true
- 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
- . size prefix
- 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
- . suffix_always is true
- 'E' => print 'e' if 32-bit form of jcxz
- 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
- 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
- 'H' => print ",pt" or ",pn" branch hint
- 'I' => honor following macro letter even in Intel mode (implemented only
- . for some of the macro letters)
- 'J' => print 'l'
- 'K' => print 'd' or 'q' if rex prefix is present.
- 'L' => print 'l' if suffix_always is true
- 'N' => print 'n' if instruction has no wait "prefix"
- 'O' => print 'd' or 'o' (or 'q' in Intel mode)
- 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
- . or suffix_always is true. print 'q' if rex prefix is present.
- 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always
- . is true
- 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
- 'S' => print 'w', 'l' or 'q' if suffix_always is true
- 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
- 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
- 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
- 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
- 'X' => print 's', 'd' depending on data16 prefix (for XMM)
- 'Y' => 'q' if instruction has an REX 64bit overwrite prefix
- 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
-
- Many of the above letters print nothing in Intel mode. See "putop"
- for the details.
-
- Braces '{' and '}', and vertical bars '|', indicate alternative
- mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel
- modes. In cases where there are only two alternatives, the X86_64
- instruction is reserved, and "(bad)" is printed.
-*/
-
-static const struct dis386 dis386[] = {
- /* 00 */
- { "addB", { Eb, Gb } },
- { "addS", { Ev, Gv } },
- { "addB", { Gb, Eb } },
- { "addS", { Gv, Ev } },
- { "addB", { AL, Ib } },
- { "addS", { eAX, Iv } },
- { "push{T|}", { es } },
- { "pop{T|}", { es } },
- /* 08 */
- { "orB", { Eb, Gb } },
- { "orS", { Ev, Gv } },
- { "orB", { Gb, Eb } },
- { "orS", { Gv, Ev } },
- { "orB", { AL, Ib } },
- { "orS", { eAX, Iv } },
- { "push{T|}", { cs } },
- { "(bad)", { XX } }, /* 0x0f extended opcode escape */
- /* 10 */
- { "adcB", { Eb, Gb } },
- { "adcS", { Ev, Gv } },
- { "adcB", { Gb, Eb } },
- { "adcS", { Gv, Ev } },
- { "adcB", { AL, Ib } },
- { "adcS", { eAX, Iv } },
- { "push{T|}", { ss } },
- { "pop{T|}", { ss } },
- /* 18 */
- { "sbbB", { Eb, Gb } },
- { "sbbS", { Ev, Gv } },
- { "sbbB", { Gb, Eb } },
- { "sbbS", { Gv, Ev } },
- { "sbbB", { AL, Ib } },
- { "sbbS", { eAX, Iv } },
- { "push{T|}", { ds } },
- { "pop{T|}", { ds } },
- /* 20 */
- { "andB", { Eb, Gb } },
- { "andS", { Ev, Gv } },
- { "andB", { Gb, Eb } },
- { "andS", { Gv, Ev } },
- { "andB", { AL, Ib } },
- { "andS", { eAX, Iv } },
- { "(bad)", { XX } }, /* SEG ES prefix */
- { "daa{|}", { XX } },
- /* 28 */
- { "subB", { Eb, Gb } },
- { "subS", { Ev, Gv } },
- { "subB", { Gb, Eb } },
- { "subS", { Gv, Ev } },
- { "subB", { AL, Ib } },
- { "subS", { eAX, Iv } },
- { "(bad)", { XX } }, /* SEG CS prefix */
- { "das{|}", { XX } },
- /* 30 */
- { "xorB", { Eb, Gb } },
- { "xorS", { Ev, Gv } },
- { "xorB", { Gb, Eb } },
- { "xorS", { Gv, Ev } },
- { "xorB", { AL, Ib } },
- { "xorS", { eAX, Iv } },
- { "(bad)", { XX } }, /* SEG SS prefix */
- { "aaa{|}", { XX } },
- /* 38 */
- { "cmpB", { Eb, Gb } },
- { "cmpS", { Ev, Gv } },
- { "cmpB", { Gb, Eb } },
- { "cmpS", { Gv, Ev } },
- { "cmpB", { AL, Ib } },
- { "cmpS", { eAX, Iv } },
- { "(bad)", { XX } }, /* SEG DS prefix */
- { "aas{|}", { XX } },
- /* 40 */
- { "inc{S|}", { RMeAX } },
- { "inc{S|}", { RMeCX } },
- { "inc{S|}", { RMeDX } },
- { "inc{S|}", { RMeBX } },
- { "inc{S|}", { RMeSP } },
- { "inc{S|}", { RMeBP } },
- { "inc{S|}", { RMeSI } },
- { "inc{S|}", { RMeDI } },
- /* 48 */
- { "dec{S|}", { RMeAX } },
- { "dec{S|}", { RMeCX } },
- { "dec{S|}", { RMeDX } },
- { "dec{S|}", { RMeBX } },
- { "dec{S|}", { RMeSP } },
- { "dec{S|}", { RMeBP } },
- { "dec{S|}", { RMeSI } },
- { "dec{S|}", { RMeDI } },
- /* 50 */
- { "pushV", { RMrAX } },
- { "pushV", { RMrCX } },
- { "pushV", { RMrDX } },
- { "pushV", { RMrBX } },
- { "pushV", { RMrSP } },
- { "pushV", { RMrBP } },
- { "pushV", { RMrSI } },
- { "pushV", { RMrDI } },
- /* 58 */
- { "popV", { RMrAX } },
- { "popV", { RMrCX } },
- { "popV", { RMrDX } },
- { "popV", { RMrBX } },
- { "popV", { RMrSP } },
- { "popV", { RMrBP } },
- { "popV", { RMrSI } },
- { "popV", { RMrDI } },
- /* 60 */
- { X86_64_0 },
- { X86_64_1 },
- { X86_64_2 },
- { X86_64_3 },
- { "(bad)", { XX } }, /* seg fs */
- { "(bad)", { XX } }, /* seg gs */
- { "(bad)", { XX } }, /* op size prefix */
- { "(bad)", { XX } }, /* adr size prefix */
- /* 68 */
- { "pushT", { Iq } },
- { "imulS", { Gv, Ev, Iv } },
- { "pushT", { sIb } },
- { "imulS", { Gv, Ev, sIb } },
- { "ins{b||b|}", { Ybr, indirDX } },
- { "ins{R||G|}", { Yzr, indirDX } },
- { "outs{b||b|}", { indirDXr, Xb } },
- { "outs{R||G|}", { indirDXr, Xz } },
- /* 70 */
- { "joH", { Jb, XX, cond_jump_flag } },
- { "jnoH", { Jb, XX, cond_jump_flag } },
- { "jbH", { Jb, XX, cond_jump_flag } },
- { "jaeH", { Jb, XX, cond_jump_flag } },
- { "jeH", { Jb, XX, cond_jump_flag } },
- { "jneH", { Jb, XX, cond_jump_flag } },
- { "jbeH", { Jb, XX, cond_jump_flag } },
- { "jaH", { Jb, XX, cond_jump_flag } },
- /* 78 */
- { "jsH", { Jb, XX, cond_jump_flag } },
- { "jnsH", { Jb, XX, cond_jump_flag } },
- { "jpH", { Jb, XX, cond_jump_flag } },
- { "jnpH", { Jb, XX, cond_jump_flag } },
- { "jlH", { Jb, XX, cond_jump_flag } },
- { "jgeH", { Jb, XX, cond_jump_flag } },
- { "jleH", { Jb, XX, cond_jump_flag } },
- { "jgH", { Jb, XX, cond_jump_flag } },
- /* 80 */
- { GRP1b },
- { GRP1S },
- { "(bad)", { XX } },
- { GRP1Ss },
- { "testB", { Eb, Gb } },
- { "testS", { Ev, Gv } },
- { "xchgB", { Eb, Gb } },
- { "xchgS", { Ev, Gv } },
- /* 88 */
- { "movB", { Eb, Gb } },
- { "movS", { Ev, Gv } },
- { "movB", { Gb, Eb } },
- { "movS", { Gv, Ev } },
- { "movD", { Sv, Sw } },
- { "leaS", { Gv, M } },
- { "movD", { Sw, Sv } },
- { GRP1a },
- /* 90 */
- { PREGRP38 },
- { "xchgS", { RMeCX, eAX } },
- { "xchgS", { RMeDX, eAX } },
- { "xchgS", { RMeBX, eAX } },
- { "xchgS", { RMeSP, eAX } },
- { "xchgS", { RMeBP, eAX } },
- { "xchgS", { RMeSI, eAX } },
- { "xchgS", { RMeDI, eAX } },
- /* 98 */
- { "cW{t||t|}R", { XX } },
- { "cR{t||t|}O", { XX } },
- { "Jcall{T|}", { Ap } },
- { "(bad)", { XX } }, /* fwait */
- { "pushfT", { XX } },
- { "popfT", { XX } },
- { "sahf{|}", { XX } },
- { "lahf{|}", { XX } },
- /* a0 */
- { "movB", { AL, Ob } },
- { "movS", { eAX, Ov } },
- { "movB", { Ob, AL } },
- { "movS", { Ov, eAX } },
- { "movs{b||b|}", { Ybr, Xb } },
- { "movs{R||R|}", { Yvr, Xv } },
- { "cmps{b||b|}", { Xb, Yb } },
- { "cmps{R||R|}", { Xv, Yv } },
- /* a8 */
- { "testB", { AL, Ib } },
- { "testS", { eAX, Iv } },
- { "stosB", { Ybr, AL } },
- { "stosS", { Yvr, eAX } },
- { "lodsB", { ALr, Xb } },
- { "lodsS", { eAXr, Xv } },
- { "scasB", { AL, Yb } },
- { "scasS", { eAX, Yv } },
- /* b0 */
- { "movB", { RMAL, Ib } },
- { "movB", { RMCL, Ib } },
- { "movB", { RMDL, Ib } },
- { "movB", { RMBL, Ib } },
- { "movB", { RMAH, Ib } },
- { "movB", { RMCH, Ib } },
- { "movB", { RMDH, Ib } },
- { "movB", { RMBH, Ib } },
- /* b8 */
- { "movS", { RMeAX, Iv64 } },
- { "movS", { RMeCX, Iv64 } },
- { "movS", { RMeDX, Iv64 } },
- { "movS", { RMeBX, Iv64 } },
- { "movS", { RMeSP, Iv64 } },
- { "movS", { RMeBP, Iv64 } },
- { "movS", { RMeSI, Iv64 } },
- { "movS", { RMeDI, Iv64 } },
- /* c0 */
- { GRP2b },
- { GRP2S },
- { "retT", { Iw } },
- { "retT", { XX } },
- { "les{S|}", { Gv, Mp } },
- { "ldsS", { Gv, Mp } },
- { GRP11_C6 },
- { GRP11_C7 },
- /* c8 */
- { "enterT", { Iw, Ib } },
- { "leaveT", { XX } },
- { "lretP", { Iw } },
- { "lretP", { XX } },
- { "int3", { XX } },
- { "int", { Ib } },
- { "into{|}", { XX } },
- { "iretP", { XX } },
- /* d0 */
- { GRP2b_one },
- { GRP2S_one },
- { GRP2b_cl },
- { GRP2S_cl },
- { "aam{|}", { sIb } },
- { "aad{|}", { sIb } },
- { "(bad)", { XX } },
- { "xlat", { DSBX } },
- /* d8 */
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- { FLOAT },
- /* e0 */
- { "loopneFH", { Jb, XX, loop_jcxz_flag } },
- { "loopeFH", { Jb, XX, loop_jcxz_flag } },
- { "loopFH", { Jb, XX, loop_jcxz_flag } },
- { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
- { "inB", { AL, Ib } },
- { "inG", { zAX, Ib } },
- { "outB", { Ib, AL } },
- { "outG", { Ib, zAX } },
- /* e8 */
- { "callT", { Jv } },
- { "jmpT", { Jv } },
- { "Jjmp{T|}", { Ap } },
- { "jmp", { Jb } },
- { "inB", { AL, indirDX } },
- { "inG", { zAX, indirDX } },
- { "outB", { indirDX, AL } },
- { "outG", { indirDX, zAX } },
- /* f0 */
- { "(bad)", { XX } }, /* lock prefix */
- { "icebp", { XX } },
- { "(bad)", { XX } }, /* repne */
- { "(bad)", { XX } }, /* repz */
- { "hlt", { XX } },
- { "cmc", { XX } },
- { GRP3b },
- { GRP3S },
- /* f8 */
- { "clc", { XX } },
- { "stc", { XX } },
- { "cli", { XX } },
- { "sti", { XX } },
- { "cld", { XX } },
- { "std", { XX } },
- { GRP4 },
- { GRP5 },
-};
-
-static const struct dis386 dis386_twobyte[] = {
- /* 00 */
- { GRP6 },
- { GRP7 },
- { "larS", { Gv, Ew } },
- { "lslS", { Gv, Ew } },
- { "(bad)", { XX } },
- { "syscall", { XX } },
- { "clts", { XX } },
- { "sysretP", { XX } },
- /* 08 */
- { "invd", { XX } },
- { "wbinvd", { XX } },
- { "(bad)", { XX } },
- { "ud2a", { XX } },
- { "(bad)", { XX } },
- { GRPAMD },
- { "femms", { XX } },
- { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
- /* 10 */
- { PREGRP8 },
- { PREGRP9 },
- { PREGRP30 },
- { "movlpX", { EXq, XM, { SIMD_Fixup, 'h' } } },
- { "unpcklpX", { XM, EXq } },
- { "unpckhpX", { XM, EXq } },
- { PREGRP31 },
- { "movhpX", { EXq, XM, { SIMD_Fixup, 'l' } } },
- /* 18 */
- { GRP16 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "nopQ", { Ev } },
- /* 20 */
- { "movZ", { Rm, Cm } },
- { "movZ", { Rm, Dm } },
- { "movZ", { Cm, Rm } },
- { "movZ", { Dm, Rm } },
- { "movL", { Rd, Td } },
- { "(bad)", { XX } },
- { "movL", { Td, Rd } },
- { "(bad)", { XX } },
- /* 28 */
- { "movapX", { XM, EXx } },
- { "movapX", { EXx, XM } },
- { PREGRP2 },
- { PREGRP33 },
- { PREGRP4 },
- { PREGRP3 },
- { PREGRP93 },
- { PREGRP94 },
- /* 30 */
- { "wrmsr", { XX } },
- { "rdtsc", { XX } },
- { "rdmsr", { XX } },
- { "rdpmc", { XX } },
- { "sysenter", { XX } },
- { "sysexit", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 38 */
- { THREE_BYTE_0 },
- { "(bad)", { XX } },
- { THREE_BYTE_1 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 40 */
- { "cmovo", { Gv, Ev } },
- { "cmovno", { Gv, Ev } },
- { "cmovb", { Gv, Ev } },
- { "cmovae", { Gv, Ev } },
- { "cmove", { Gv, Ev } },
- { "cmovne", { Gv, Ev } },
- { "cmovbe", { Gv, Ev } },
- { "cmova", { Gv, Ev } },
- /* 48 */
- { "cmovs", { Gv, Ev } },
- { "cmovns", { Gv, Ev } },
- { "cmovp", { Gv, Ev } },
- { "cmovnp", { Gv, Ev } },
- { "cmovl", { Gv, Ev } },
- { "cmovge", { Gv, Ev } },
- { "cmovle", { Gv, Ev } },
- { "cmovg", { Gv, Ev } },
- /* 50 */
- { "movmskpX", { Gdq, XS } },
- { PREGRP13 },
- { PREGRP12 },
- { PREGRP11 },
- { "andpX", { XM, EXx } },
- { "andnpX", { XM, EXx } },
- { "orpX", { XM, EXx } },
- { "xorpX", { XM, EXx } },
- /* 58 */
- { PREGRP0 },
- { PREGRP10 },
- { PREGRP17 },
- { PREGRP16 },
- { PREGRP14 },
- { PREGRP7 },
- { PREGRP5 },
- { PREGRP6 },
- /* 60 */
- { PREGRP95 },
- { PREGRP96 },
- { PREGRP97 },
- { "packsswb", { MX, EM } },
- { "pcmpgtb", { MX, EM } },
- { "pcmpgtw", { MX, EM } },
- { "pcmpgtd", { MX, EM } },
- { "packuswb", { MX, EM } },
- /* 68 */
- { "punpckhbw", { MX, EM } },
- { "punpckhwd", { MX, EM } },
- { "punpckhdq", { MX, EM } },
- { "packssdw", { MX, EM } },
- { PREGRP26 },
- { PREGRP24 },
- { "movd", { MX, Edq } },
- { PREGRP19 },
- /* 70 */
- { PREGRP22 },
- { GRP12 },
- { GRP13 },
- { GRP14 },
- { "pcmpeqb", { MX, EM } },
- { "pcmpeqw", { MX, EM } },
- { "pcmpeqd", { MX, EM } },
- { "emms", { XX } },
- /* 78 */
- { PREGRP34 },
- { PREGRP35 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP28 },
- { PREGRP29 },
- { PREGRP23 },
- { PREGRP20 },
- /* 80 */
- { "joH", { Jv, XX, cond_jump_flag } },
- { "jnoH", { Jv, XX, cond_jump_flag } },
- { "jbH", { Jv, XX, cond_jump_flag } },
- { "jaeH", { Jv, XX, cond_jump_flag } },
- { "jeH", { Jv, XX, cond_jump_flag } },
- { "jneH", { Jv, XX, cond_jump_flag } },
- { "jbeH", { Jv, XX, cond_jump_flag } },
- { "jaH", { Jv, XX, cond_jump_flag } },
- /* 88 */
- { "jsH", { Jv, XX, cond_jump_flag } },
- { "jnsH", { Jv, XX, cond_jump_flag } },
- { "jpH", { Jv, XX, cond_jump_flag } },
- { "jnpH", { Jv, XX, cond_jump_flag } },
- { "jlH", { Jv, XX, cond_jump_flag } },
- { "jgeH", { Jv, XX, cond_jump_flag } },
- { "jleH", { Jv, XX, cond_jump_flag } },
- { "jgH", { Jv, XX, cond_jump_flag } },
- /* 90 */
- { "seto", { Eb } },
- { "setno", { Eb } },
- { "setb", { Eb } },
- { "setae", { Eb } },
- { "sete", { Eb } },
- { "setne", { Eb } },
- { "setbe", { Eb } },
- { "seta", { Eb } },
- /* 98 */
- { "sets", { Eb } },
- { "setns", { Eb } },
- { "setp", { Eb } },
- { "setnp", { Eb } },
- { "setl", { Eb } },
- { "setge", { Eb } },
- { "setle", { Eb } },
- { "setg", { Eb } },
- /* a0 */
- { "pushT", { fs } },
- { "popT", { fs } },
- { "cpuid", { XX } },
- { "btS", { Ev, Gv } },
- { "shldS", { Ev, Gv, Ib } },
- { "shldS", { Ev, Gv, CL } },
- { GRPPADLCK2 },
- { GRPPADLCK1 },
- /* a8 */
- { "pushT", { gs } },
- { "popT", { gs } },
- { "rsm", { XX } },
- { "btsS", { Ev, Gv } },
- { "shrdS", { Ev, Gv, Ib } },
- { "shrdS", { Ev, Gv, CL } },
- { GRP15 },
- { "imulS", { Gv, Ev } },
- /* b0 */
- { "cmpxchgB", { Eb, Gb } },
- { "cmpxchgS", { Ev, Gv } },
- { "lssS", { Gv, Mp } },
- { "btrS", { Ev, Gv } },
- { "lfsS", { Gv, Mp } },
- { "lgsS", { Gv, Mp } },
- { "movz{bR|x|bR|x}", { Gv, Eb } },
- { "movz{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
- /* b8 */
- { PREGRP37 },
- { "ud2b", { XX } },
- { GRP8 },
- { "btcS", { Ev, Gv } },
- { PREGRP107 },
- { PREGRP36 },
- { "movs{bR|x|bR|x}", { Gv, Eb } },
- { "movs{wR|x|wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
- /* c0 */
- { "xaddB", { Eb, Gb } },
- { "xaddS", { Ev, Gv } },
- { PREGRP1 },
- { "movntiS", { Ev, Gv } },
- { "pinsrw", { MX, Edqw, Ib } },
- { "pextrw", { Gdq, MS, Ib } },
- { "shufpX", { XM, EXx, Ib } },
- { GRP9 },
- /* c8 */
- { "bswap", { RMeAX } },
- { "bswap", { RMeCX } },
- { "bswap", { RMeDX } },
- { "bswap", { RMeBX } },
- { "bswap", { RMeSP } },
- { "bswap", { RMeBP } },
- { "bswap", { RMeSI } },
- { "bswap", { RMeDI } },
- /* d0 */
- { PREGRP27 },
- { "psrlw", { MX, EM } },
- { "psrld", { MX, EM } },
- { "psrlq", { MX, EM } },
- { "paddq", { MX, EM } },
- { "pmullw", { MX, EM } },
- { PREGRP21 },
- { "pmovmskb", { Gdq, MS } },
- /* d8 */
- { "psubusb", { MX, EM } },
- { "psubusw", { MX, EM } },
- { "pminub", { MX, EM } },
- { "pand", { MX, EM } },
- { "paddusb", { MX, EM } },
- { "paddusw", { MX, EM } },
- { "pmaxub", { MX, EM } },
- { "pandn", { MX, EM } },
- /* e0 */
- { "pavgb", { MX, EM } },
- { "psraw", { MX, EM } },
- { "psrad", { MX, EM } },
- { "pavgw", { MX, EM } },
- { "pmulhuw", { MX, EM } },
- { "pmulhw", { MX, EM } },
- { PREGRP15 },
- { PREGRP25 },
- /* e8 */
- { "psubsb", { MX, EM } },
- { "psubsw", { MX, EM } },
- { "pminsw", { MX, EM } },
- { "por", { MX, EM } },
- { "paddsb", { MX, EM } },
- { "paddsw", { MX, EM } },
- { "pmaxsw", { MX, EM } },
- { "pxor", { MX, EM } },
- /* f0 */
- { PREGRP32 },
- { "psllw", { MX, EM } },
- { "pslld", { MX, EM } },
- { "psllq", { MX, EM } },
- { "pmuludq", { MX, EM } },
- { "pmaddwd", { MX, EM } },
- { "psadbw", { MX, EM } },
- { PREGRP18 },
- /* f8 */
- { "psubb", { MX, EM } },
- { "psubw", { MX, EM } },
- { "psubd", { MX, EM } },
- { "psubq", { MX, EM } },
- { "paddb", { MX, EM } },
- { "paddw", { MX, EM } },
- { "paddd", { MX, EM } },
- { "(bad)", { XX } },
-};
-
-static const unsigned char onebyte_has_modrm[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
- /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
- /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
- /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
- /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
- /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
- /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
- /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
- /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-static const unsigned char twobyte_has_modrm[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
- /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */
- /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
- /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
- /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
- /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
- /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
- /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
- /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
- /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
- /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
- /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-static const unsigned char twobyte_uses_DATA_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
- /* 70 */ 1,0,0,0,0,0,0,0,1,1,0,0,1,1,1,1, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-static const unsigned char twobyte_uses_REPNZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,1,0,0,0,0,0,0,1,1,1,0,1,1,1,1, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 1,0,0,0,0,0,0,0,1,1,0,0,1,1,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-static const unsigned char twobyte_uses_REPZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,1,1,1,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1, /* 6f */
- /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,1,0,0,0,1,1,0,0, /* bf */
- /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 38 XX uses DATA prefix. */
-static const unsigned char threebyte_0x38_uses_DATA_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0, /* 0f */
- /* 10 */ 1,0,0,0,1,1,0,1,0,0,0,0,1,1,1,0, /* 1f */
- /* 20 */ 1,1,1,1,1,1,0,0,1,1,1,1,0,0,0,0, /* 2f */
- /* 30 */ 1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1, /* 3f */
- /* 40 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 38 XX uses REPNZ prefix. */
-static const unsigned char threebyte_0x38_uses_REPNZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 1,1,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 38 XX uses REPZ prefix. */
-static const unsigned char threebyte_0x38_uses_REPZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 3a XX uses DATA prefix. */
-static const unsigned char threebyte_0x3a_uses_DATA_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1, /* 0f */
- /* 10 */ 0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 3a XX uses REPNZ prefix. */
-static const unsigned char threebyte_0x3a_uses_REPNZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-/* This is used to determine if opcode 0f 3a XX uses REPZ prefix. */
-static const unsigned char threebyte_0x3a_uses_REPZ_prefix[256] = {
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
- /* ------------------------------- */
- /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
- /* 10 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */
- /* 20 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
- /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
- /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
- /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
- /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
- /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
- /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
- /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
- /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
- /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
- /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
- /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
- /* ------------------------------- */
- /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
-};
-
-static char obuf[100];
-static char *obufp;
-static char scratchbuf[100];
-static unsigned char *start_codep;
-static unsigned char *insn_codep;
-static unsigned char *codep;
-static disassemble_info *the_info;
-static struct
- {
- int mod;
- int reg;
- int rm;
- }
-modrm;
-static unsigned char need_modrm;
-
-/* If we are accessing mod/rm/reg without need_modrm set, then the
- values are stale. Hitting this abort likely indicates that you
- need to update onebyte_has_modrm or twobyte_has_modrm. */
-#define MODRM_CHECK if (!need_modrm) abort ()
-
-static const char * const *names64;
-static const char * const *names32;
-static const char * const *names16;
-static const char * const *names8;
-static const char * const *names8rex;
-static const char * const *names_seg;
-static const char * const *index16;
-
-static const char * const intel_names64[] = {
- "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
-};
-static const char * const intel_names32[] = {
- "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
- "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
-};
-static const char * const intel_names16[] = {
- "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
- "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
-};
-static const char * const intel_names8[] = {
- "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
-};
-static const char * const intel_names8rex[] = {
- "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
- "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
-};
-static const char * const intel_names_seg[] = {
- "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
-};
-static const char * const intel_index16[] = {
- "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
-};
-
-static const char * const att_names64[] = {
- "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
-};
-static const char * const att_names32[] = {
- "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
- "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
-};
-static const char * const att_names16[] = {
- "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
- "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
-};
-static const char * const att_names8[] = {
- "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
-};
-static const char * const att_names8rex[] = {
- "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
- "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
-};
-static const char * const att_names_seg[] = {
- "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
-};
-static const char * const att_index16[] = {
- "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
-};
-
-static const struct dis386 grps[][8] = {
- /* GRP1a */
- {
- { "popU", { stackEv } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRP1b */
- {
- { "addA", { Eb, Ib } },
- { "orA", { Eb, Ib } },
- { "adcA", { Eb, Ib } },
- { "sbbA", { Eb, Ib } },
- { "andA", { Eb, Ib } },
- { "subA", { Eb, Ib } },
- { "xorA", { Eb, Ib } },
- { "cmpA", { Eb, Ib } },
- },
- /* GRP1S */
- {
- { "addQ", { Ev, Iv } },
- { "orQ", { Ev, Iv } },
- { "adcQ", { Ev, Iv } },
- { "sbbQ", { Ev, Iv } },
- { "andQ", { Ev, Iv } },
- { "subQ", { Ev, Iv } },
- { "xorQ", { Ev, Iv } },
- { "cmpQ", { Ev, Iv } },
- },
- /* GRP1Ss */
- {
- { "addQ", { Ev, sIb } },
- { "orQ", { Ev, sIb } },
- { "adcQ", { Ev, sIb } },
- { "sbbQ", { Ev, sIb } },
- { "andQ", { Ev, sIb } },
- { "subQ", { Ev, sIb } },
- { "xorQ", { Ev, sIb } },
- { "cmpQ", { Ev, sIb } },
- },
- /* GRP2b */
- {
- { "rolA", { Eb, Ib } },
- { "rorA", { Eb, Ib } },
- { "rclA", { Eb, Ib } },
- { "rcrA", { Eb, Ib } },
- { "shlA", { Eb, Ib } },
- { "shrA", { Eb, Ib } },
- { "(bad)", { XX } },
- { "sarA", { Eb, Ib } },
- },
- /* GRP2S */
- {
- { "rolQ", { Ev, Ib } },
- { "rorQ", { Ev, Ib } },
- { "rclQ", { Ev, Ib } },
- { "rcrQ", { Ev, Ib } },
- { "shlQ", { Ev, Ib } },
- { "shrQ", { Ev, Ib } },
- { "(bad)", { XX } },
- { "sarQ", { Ev, Ib } },
- },
- /* GRP2b_one */
- {
- { "rolA", { Eb, I1 } },
- { "rorA", { Eb, I1 } },
- { "rclA", { Eb, I1 } },
- { "rcrA", { Eb, I1 } },
- { "shlA", { Eb, I1 } },
- { "shrA", { Eb, I1 } },
- { "(bad)", { XX } },
- { "sarA", { Eb, I1 } },
- },
- /* GRP2S_one */
- {
- { "rolQ", { Ev, I1 } },
- { "rorQ", { Ev, I1 } },
- { "rclQ", { Ev, I1 } },
- { "rcrQ", { Ev, I1 } },
- { "shlQ", { Ev, I1 } },
- { "shrQ", { Ev, I1 } },
- { "(bad)", { XX } },
- { "sarQ", { Ev, I1 } },
- },
- /* GRP2b_cl */
- {
- { "rolA", { Eb, CL } },
- { "rorA", { Eb, CL } },
- { "rclA", { Eb, CL } },
- { "rcrA", { Eb, CL } },
- { "shlA", { Eb, CL } },
- { "shrA", { Eb, CL } },
- { "(bad)", { XX } },
- { "sarA", { Eb, CL } },
- },
- /* GRP2S_cl */
- {
- { "rolQ", { Ev, CL } },
- { "rorQ", { Ev, CL } },
- { "rclQ", { Ev, CL } },
- { "rcrQ", { Ev, CL } },
- { "shlQ", { Ev, CL } },
- { "shrQ", { Ev, CL } },
- { "(bad)", { XX } },
- { "sarQ", { Ev, CL } },
- },
- /* GRP3b */
- {
- { "testA", { Eb, Ib } },
- { "(bad)", { Eb } },
- { "notA", { Eb } },
- { "negA", { Eb } },
- { "mulA", { Eb } }, /* Don't print the implicit %al register, */
- { "imulA", { Eb } }, /* to distinguish these opcodes from other */
- { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
- { "idivA", { Eb } }, /* and idiv for consistency. */
- },
- /* GRP3S */
- {
- { "testQ", { Ev, Iv } },
- { "(bad)", { XX } },
- { "notQ", { Ev } },
- { "negQ", { Ev } },
- { "mulQ", { Ev } }, /* Don't print the implicit register. */
- { "imulQ", { Ev } },
- { "divQ", { Ev } },
- { "idivQ", { Ev } },
- },
- /* GRP4 */
- {
- { "incA", { Eb } },
- { "decA", { Eb } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRP5 */
- {
- { "incQ", { Ev } },
- { "decQ", { Ev } },
- { "callT", { indirEv } },
- { "JcallT", { indirEp } },
- { "jmpT", { indirEv } },
- { "JjmpT", { indirEp } },
- { "pushU", { stackEv } },
- { "(bad)", { XX } },
- },
- /* GRP6 */
- {
- { "sldtD", { Sv } },
- { "strD", { Sv } },
- { "lldt", { Ew } },
- { "ltr", { Ew } },
- { "verr", { Ew } },
- { "verw", { Ew } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRP7 */
- {
- { "sgdt{Q|IQ||}", { { VMX_Fixup, 0 } } },
- { "sidt{Q|IQ||}", { { PNI_Fixup, 0 } } },
- { "lgdt{Q|Q||}", { M } },
- { "lidt{Q|Q||}", { { SVME_Fixup, 0 } } },
- { "smswD", { Sv } },
- { "(bad)", { XX } },
- { "lmsw", { Ew } },
- { "invlpg", { { INVLPG_Fixup, w_mode } } },
- },
- /* GRP8 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "btQ", { Ev, Ib } },
- { "btsQ", { Ev, Ib } },
- { "btrQ", { Ev, Ib } },
- { "btcQ", { Ev, Ib } },
- },
- /* GRP9 */
- {
- { "(bad)", { XX } },
- { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "", { VM } }, /* See OP_VMX. */
- { "vmptrst", { Mq } },
- },
- /* GRP11_C6 */
- {
- { "movA", { Eb, Ib } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRP11_C7 */
- {
- { "movQ", { Ev, Iv } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRP12 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "psrlw", { MS, Ib } },
- { "(bad)", { XX } },
- { "psraw", { MS, Ib } },
- { "(bad)", { XX } },
- { "psllw", { MS, Ib } },
- { "(bad)", { XX } },
- },
- /* GRP13 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "psrld", { MS, Ib } },
- { "(bad)", { XX } },
- { "psrad", { MS, Ib } },
- { "(bad)", { XX } },
- { "pslld", { MS, Ib } },
- { "(bad)", { XX } },
- },
- /* GRP14 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "psrlq", { MS, Ib } },
- { "psrldq", { MS, Ib } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "psllq", { MS, Ib } },
- { "pslldq", { MS, Ib } },
- },
- /* GRP15 */
- {
- { "fxsave", { Ev } },
- { "fxrstor", { Ev } },
- { "ldmxcsr", { Ev } },
- { "stmxcsr", { Ev } },
- { "(bad)", { XX } },
- { "lfence", { { OP_0fae, 0 } } },
- { "mfence", { { OP_0fae, 0 } } },
- { "clflush", { { OP_0fae, 0 } } },
- },
- /* GRP16 */
- {
- { "prefetchnta", { Ev } },
- { "prefetcht0", { Ev } },
- { "prefetcht1", { Ev } },
- { "prefetcht2", { Ev } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRPAMD */
- {
- { "prefetch", { Eb } },
- { "prefetchw", { Eb } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* GRPPADLCK1 */
- {
- { "xstore-rng", { { OP_0f07, 0 } } },
- { "xcrypt-ecb", { { OP_0f07, 0 } } },
- { "xcrypt-cbc", { { OP_0f07, 0 } } },
- { "xcrypt-ctr", { { OP_0f07, 0 } } },
- { "xcrypt-cfb", { { OP_0f07, 0 } } },
- { "xcrypt-ofb", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- },
- /* GRPPADLCK2 */
- {
- { "montmul", { { OP_0f07, 0 } } },
- { "xsha1", { { OP_0f07, 0 } } },
- { "xsha256", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- { "(bad)", { { OP_0f07, 0 } } },
- }
-};
-
-static const struct dis386 prefix_user_table[][4] = {
- /* PREGRP0 */
- {
- { "addps", { XM, EXx } },
- { "addss", { XM, EXd } },
- { "addpd", { XM, EXx } },
- { "addsd", { XM, EXq } },
- },
- /* PREGRP1 */
- {
- { "", { XM, EXx, OPSIMD } }, /* See OP_SIMD_SUFFIX. */
- { "", { XM, EXx, OPSIMD } },
- { "", { XM, EXx, OPSIMD } },
- { "", { XM, EXx, OPSIMD } },
- },
- /* PREGRP2 */
- {
- { "cvtpi2ps", { XM, EMC } },
- { "cvtsi2ssY", { XM, Ev } },
- { "cvtpi2pd", { XM, EMC } },
- { "cvtsi2sdY", { XM, Ev } },
- },
- /* PREGRP3 */
- {
- { "cvtps2pi", { MXC, EXx } },
- { "cvtss2siY", { Gv, EXx } },
- { "cvtpd2pi", { MXC, EXx } },
- { "cvtsd2siY", { Gv, EXx } },
- },
- /* PREGRP4 */
- {
- { "cvttps2pi", { MXC, EXx } },
- { "cvttss2siY", { Gv, EXx } },
- { "cvttpd2pi", { MXC, EXx } },
- { "cvttsd2siY", { Gv, EXx } },
- },
- /* PREGRP5 */
- {
- { "divps", { XM, EXx } },
- { "divss", { XM, EXx } },
- { "divpd", { XM, EXx } },
- { "divsd", { XM, EXx } },
- },
- /* PREGRP6 */
- {
- { "maxps", { XM, EXx } },
- { "maxss", { XM, EXx } },
- { "maxpd", { XM, EXx } },
- { "maxsd", { XM, EXx } },
- },
- /* PREGRP7 */
- {
- { "minps", { XM, EXx } },
- { "minss", { XM, EXx } },
- { "minpd", { XM, EXx } },
- { "minsd", { XM, EXx } },
- },
- /* PREGRP8 */
- {
- { "movups", { XM, EXx } },
- { "movss", { XM, EXx } },
- { "movupd", { XM, EXx } },
- { "movsd", { XM, EXx } },
- },
- /* PREGRP9 */
- {
- { "movups", { EXx, XM } },
- { "movss", { EXx, XM } },
- { "movupd", { EXx, XM } },
- { "movsd", { EXx, XM } },
- },
- /* PREGRP10 */
- {
- { "mulps", { XM, EXx } },
- { "mulss", { XM, EXx } },
- { "mulpd", { XM, EXx } },
- { "mulsd", { XM, EXx } },
- },
- /* PREGRP11 */
- {
- { "rcpps", { XM, EXx } },
- { "rcpss", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP12 */
- {
- { "rsqrtps",{ XM, EXx } },
- { "rsqrtss",{ XM, EXx } },
- { "(bad)", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP13 */
- {
- { "sqrtps", { XM, EXx } },
- { "sqrtss", { XM, EXx } },
- { "sqrtpd", { XM, EXx } },
- { "sqrtsd", { XM, EXx } },
- },
- /* PREGRP14 */
- {
- { "subps", { XM, EXx } },
- { "subss", { XM, EXx } },
- { "subpd", { XM, EXx } },
- { "subsd", { XM, EXx } },
- },
- /* PREGRP15 */
- {
- { "(bad)", { XM, EXx } },
- { "cvtdq2pd", { XM, EXq } },
- { "cvttpd2dq", { XM, EXx } },
- { "cvtpd2dq", { XM, EXx } },
- },
- /* PREGRP16 */
- {
- { "cvtdq2ps", { XM, EXx } },
- { "cvttps2dq", { XM, EXx } },
- { "cvtps2dq", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP17 */
- {
- { "cvtps2pd", { XM, EXq } },
- { "cvtss2sd", { XM, EXx } },
- { "cvtpd2ps", { XM, EXx } },
- { "cvtsd2ss", { XM, EXx } },
- },
- /* PREGRP18 */
- {
- { "maskmovq", { MX, MS } },
- { "(bad)", { XM, EXx } },
- { "maskmovdqu", { XM, XS } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP19 */
- {
- { "movq", { MX, EM } },
- { "movdqu", { XM, EXx } },
- { "movdqa", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP20 */
- {
- { "movq", { EM, MX } },
- { "movdqu", { EXx, XM } },
- { "movdqa", { EXx, XM } },
- { "(bad)", { EXx, XM } },
- },
- /* PREGRP21 */
- {
- { "(bad)", { EXx, XM } },
- { "movq2dq",{ XM, MS } },
- { "movq", { EXx, XM } },
- { "movdq2q",{ MX, XS } },
- },
- /* PREGRP22 */
- {
- { "pshufw", { MX, EM, Ib } },
- { "pshufhw",{ XM, EXx, Ib } },
- { "pshufd", { XM, EXx, Ib } },
- { "pshuflw",{ XM, EXx, Ib } },
- },
- /* PREGRP23 */
- {
- { "movd", { Edq, MX } },
- { "movq", { XM, EXx } },
- { "movd", { Edq, XM } },
- { "(bad)", { Ed, XM } },
- },
- /* PREGRP24 */
- {
- { "(bad)", { MX, EXx } },
- { "(bad)", { XM, EXx } },
- { "punpckhqdq", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP25 */
- {
- { "movntq", { EM, MX } },
- { "(bad)", { EM, XM } },
- { "movntdq",{ EM, XM } },
- { "(bad)", { EM, XM } },
- },
- /* PREGRP26 */
- {
- { "(bad)", { MX, EXx } },
- { "(bad)", { XM, EXx } },
- { "punpcklqdq", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- },
- /* PREGRP27 */
- {
- { "(bad)", { MX, EXx } },
- { "(bad)", { XM, EXx } },
- { "addsubpd", { XM, EXx } },
- { "addsubps", { XM, EXx } },
- },
- /* PREGRP28 */
- {
- { "(bad)", { MX, EXx } },
- { "(bad)", { XM, EXx } },
- { "haddpd", { XM, EXx } },
- { "haddps", { XM, EXx } },
- },
- /* PREGRP29 */
- {
- { "(bad)", { MX, EXx } },
- { "(bad)", { XM, EXx } },
- { "hsubpd", { XM, EXx } },
- { "hsubps", { XM, EXx } },
- },
- /* PREGRP30 */
- {
- { "movlpX", { XM, EXq, { SIMD_Fixup, 'h' } } }, /* really only 2 operands */
- { "movsldup", { XM, EXx } },
- { "movlpd", { XM, EXq } },
- { "movddup", { XM, EXq } },
- },
- /* PREGRP31 */
- {
- { "movhpX", { XM, EXq, { SIMD_Fixup, 'l' } } },
- { "movshdup", { XM, EXx } },
- { "movhpd", { XM, EXq } },
- { "(bad)", { XM, EXq } },
- },
- /* PREGRP32 */
- {
- { "(bad)", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- { "(bad)", { XM, EXx } },
- { "lddqu", { XM, M } },
- },
- /* PREGRP33 */
- {
- {"movntps", { Ev, XM } },
- {"movntss", { Ev, XM } },
- {"movntpd", { Ev, XM } },
- {"movntsd", { Ev, XM } },
- },
-
- /* PREGRP34 */
- {
- {"vmread", { Em, Gm } },
- {"(bad)", { XX } },
- {"extrq", { XS, Ib, Ib } },
- {"insertq", { XM, XS, Ib, Ib } },
- },
-
- /* PREGRP35 */
- {
- {"vmwrite", { Gm, Em } },
- {"(bad)", { XX } },
- {"extrq", { XM, XS } },
- {"insertq", { XM, XS } },
- },
-
- /* PREGRP36 */
- {
- { "bsrS", { Gv, Ev } },
- { "lzcntS", { Gv, Ev } },
- { "bsrS", { Gv, Ev } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP37 */
- {
- { "(bad)", { XX } },
- { "popcntS", { Gv, Ev } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP38 */
- {
- { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
- { "pause", { XX } },
- { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP39 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pblendvb", {XM, EXx, XMM0 } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP40 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "blendvps", {XM, EXx, XMM0 } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP41 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "blendvpd", { XM, EXx, XMM0 } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP42 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "ptest", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP43 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxbw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP44 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxbd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP45 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxbq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP46 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxwd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP47 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxwq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP48 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovsxdq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP49 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmuldq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP50 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpeqq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP51 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "movntdqa", { XM, EM } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP52 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "packusdw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP53 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxbw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP54 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxbd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP55 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxbq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP56 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxwd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP57 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxwq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP58 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmovzxdq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP59 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pminsb", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP60 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pminsd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP61 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pminuw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP62 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pminud", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP63 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmaxsb", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP64 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmaxsd", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP65 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmaxuw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP66 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmaxud", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP67 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pmulld", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP68 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "phminposuw", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP69 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "roundps", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP70 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "roundpd", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP71 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "roundss", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP72 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "roundsd", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP73 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "blendps", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP74 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "blendpd", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP75 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pblendw", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP76 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pextrb", { Edqb, XM, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP77 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pextrw", { Edqw, XM, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP78 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pextrK", { Edq, XM, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP79 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "extractps", { Edqd, XM, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP80 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pinsrb", { XM, Edqb, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP81 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "insertps", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP82 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pinsrK", { XM, Edq, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP83 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "dpps", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP84 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "dppd", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP85 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "mpsadbw", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP86 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpgtq", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP87 */
- {
- { "movbe", { Gv, Ev } },
- { "(bad)", { XX } },
- { "movbe", { Gv, Ev } },
- { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
- },
-
- /* PREGRP88 */
- {
- { "movbe", { Ev, Gv } },
- { "(bad)", { XX } },
- { "movbe", { Ev, Gv } },
- { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
- },
-
- /* PREGRP89 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpestrm", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP90 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpestri", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP91 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpistrm", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP92 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pcmpistri", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP93 */
- {
- { "ucomiss",{ XM, EXd } },
- { "(bad)", { XX } },
- { "ucomisd",{ XM, EXq } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP94 */
- {
- { "comiss", { XM, EXd } },
- { "(bad)", { XX } },
- { "comisd", { XM, EXq } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP95 */
- {
- { "punpcklbw",{ MX, EMd } },
- { "(bad)", { XX } },
- { "punpcklbw",{ MX, EMq } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP96 */
- {
- { "punpcklwd",{ MX, EMd } },
- { "(bad)", { XX } },
- { "punpcklwd",{ MX, EMq } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP97 */
- {
- { "punpckldq",{ MX, EMd } },
- { "(bad)", { XX } },
- { "punpckldq",{ MX, EMq } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP98 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pclmulqdq", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP99 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aesimc", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP100 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aesenc", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP101 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aesenclast", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP102 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aesdec", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP103 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aesdeclast", { XM, EXx } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP104 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "aeskeygenassist", { XM, EXx, Ib } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP105 */
- {
- { "andnS", { Gv, Bv, Ev } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP106 */
- {
- { "bextrS", { Gv, Ev, Bv } },
- { "sarxS", { Gv, Ev, Bv } },
- { "shlxS", { Gv, Ev, Bv } },
- { "shrxS", { Gv, Ev, Bv } },
- },
-
- /* PREGRP107 */
- {
- { "bsfS", { Gv, Ev } },
- { "tzcntS", { Gv, Ev } },
- { "bsfS", { Gv, Ev } },
- { "(bad)", { XX } },
- },
-
- /* PREGRP108 */
- {
- { "bzhi", { Gv, Ev, Bv } },
- { "pext", { Gv, Bv, Ev } },
- { "(bad)", { XX } },
- { "pdep", { Gv, Bv, Ev } },
- },
-
- /* PREGRP109 */
- {
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "rorx", { Gv, Ev, Ib } },
- },
-};
-
-static const struct dis386 x86_64_table[][2] = {
- {
- { "pusha{P|}", { XX } },
- { "(bad)", { XX } },
- },
- {
- { "popa{P|}", { XX } },
- { "(bad)", { XX } },
- },
- {
- { "bound{S|}", { Gv, Ma } },
- { "(bad)", { XX } },
- },
- {
- { "arpl", { Ew, Gw } },
- { "movs{||lq|xd}", { Gv, Ed } },
- },
-};
-
-static const struct dis386 three_byte_table[][256] = {
- /* THREE_BYTE_0 */
- {
- /* 00 */
- { "pshufb", { MX, EM } },
- { "phaddw", { MX, EM } },
- { "phaddd", { MX, EM } },
- { "phaddsw", { MX, EM } },
- { "pmaddubsw", { MX, EM } },
- { "phsubw", { MX, EM } },
- { "phsubd", { MX, EM } },
- { "phsubsw", { MX, EM } },
- /* 08 */
- { "psignb", { MX, EM } },
- { "psignw", { MX, EM } },
- { "psignd", { MX, EM } },
- { "pmulhrsw", { MX, EM } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 10 */
- { PREGRP39 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP40 },
- { PREGRP41 },
- { "(bad)", { XX } },
- { PREGRP42 },
- /* 18 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "pabsb", { MX, EM } },
- { "pabsw", { MX, EM } },
- { "pabsd", { MX, EM } },
- { "(bad)", { XX } },
- /* 20 */
- { PREGRP43 },
- { PREGRP44 },
- { PREGRP45 },
- { PREGRP46 },
- { PREGRP47 },
- { PREGRP48 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 28 */
- { PREGRP49 },
- { PREGRP50 },
- { PREGRP51 },
- { PREGRP52 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 30 */
- { PREGRP53 },
- { PREGRP54 },
- { PREGRP55 },
- { PREGRP56 },
- { PREGRP57 },
- { PREGRP58 },
- { "(bad)", { XX } },
- { PREGRP86 },
- /* 38 */
- { PREGRP59 },
- { PREGRP60 },
- { PREGRP61 },
- { PREGRP62 },
- { PREGRP63 },
- { PREGRP64 },
- { PREGRP65 },
- { PREGRP66 },
- /* 40 */
- { PREGRP67 },
- { PREGRP68 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 48 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 50 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 58 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 60 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 68 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 70 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 78 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 80 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 88 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 90 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 98 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* a0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* a8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* b0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* b8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* c0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* c8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* d0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* d8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP99 },
- { PREGRP100 },
- { PREGRP101 },
- { PREGRP102 },
- { PREGRP103 },
- /* e0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* e8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* f0 */
- { PREGRP87 },
- { PREGRP88 },
- { PREGRP105 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP108 },
- { "(bad)", { XX } },
- { PREGRP106 },
- /* f8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* THREE_BYTE_1 */
- {
- /* 00 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 08 */
- { PREGRP69 },
- { PREGRP70 },
- { PREGRP71 },
- { PREGRP72 },
- { PREGRP73 },
- { PREGRP74 },
- { PREGRP75 },
- { "palignr", { MX, EM, Ib } },
- /* 10 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP76 },
- { PREGRP77 },
- { PREGRP78 },
- { PREGRP79 },
- /* 18 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 20 */
- { PREGRP80 },
- { PREGRP81 },
- { PREGRP82 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 28 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 30 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 38 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 40 */
- { PREGRP83 },
- { PREGRP84 },
- { PREGRP85 },
- { "(bad)", { XX } },
- { PREGRP98 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 48 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 50 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 58 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 60 */
- { PREGRP89 },
- { PREGRP90 },
- { PREGRP91 },
- { PREGRP92 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 68 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 70 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 78 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 80 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 88 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 90 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* 98 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* a0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* a8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* b0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* b8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* c0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* c8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* d0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* d8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { PREGRP104 },
- /* e0 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* e8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* f0 */
- { PREGRP109 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- /* f8 */
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- }
-};
-
-#define INTERNAL_DISASSEMBLER_ERROR "<internal disassembler error>"
-
-static void
-ckprefix (void)
-{
- int newrex;
- rex = 0;
- prefixes = 0;
- used_prefixes = 0;
- rex_used = 0;
- while (1)
- {
- fetch_data(the_info, codep + 1);
- newrex = 0;
- switch (*codep)
- {
- /* REX prefixes family. */
- case 0x40:
- case 0x41:
- case 0x42:
- case 0x43:
- case 0x44:
- case 0x45:
- case 0x46:
- case 0x47:
- case 0x48:
- case 0x49:
- case 0x4a:
- case 0x4b:
- case 0x4c:
- case 0x4d:
- case 0x4e:
- case 0x4f:
- if (address_mode == mode_64bit)
- newrex = *codep;
- else
- return;
- break;
- case 0xf3:
- prefixes |= PREFIX_REPZ;
- break;
- case 0xf2:
- prefixes |= PREFIX_REPNZ;
- break;
- case 0xf0:
- prefixes |= PREFIX_LOCK;
- break;
- case 0x2e:
- prefixes |= PREFIX_CS;
- break;
- case 0x36:
- prefixes |= PREFIX_SS;
- break;
- case 0x3e:
- prefixes |= PREFIX_DS;
- break;
- case 0x26:
- prefixes |= PREFIX_ES;
- break;
- case 0x64:
- prefixes |= PREFIX_FS;
- break;
- case 0x65:
- prefixes |= PREFIX_GS;
- break;
- case 0x66:
- prefixes |= PREFIX_DATA;
- break;
- case 0x67:
- prefixes |= PREFIX_ADDR;
- break;
- case FWAIT_OPCODE:
- /* fwait is really an instruction. If there are prefixes
- before the fwait, they belong to the fwait, *not* to the
- following instruction. */
- if (prefixes || rex)
- {
- prefixes |= PREFIX_FWAIT;
- codep++;
- return;
- }
- prefixes = PREFIX_FWAIT;
- break;
- default:
- return;
- }
- /* Rex is ignored when followed by another prefix. */
- if (rex)
- {
- rex_used = rex;
- return;
- }
- rex = newrex;
- codep++;
- }
-}
-
-static void
-ckvexprefix (void)
-{
- int op, vex2, vex3, newrex = 0, newpfx = prefixes;
-
- if (address_mode == mode_16bit) {
- return;
- }
-
- fetch_data(the_info, codep + 1);
- op = *codep;
-
- if (op != 0xc4 && op != 0xc5) {
- return;
- }
-
- fetch_data(the_info, codep + 2);
- vex2 = codep[1];
-
- if (address_mode == mode_32bit && (vex2 & 0xc0) != 0xc0) {
- return;
- }
-
- if (op == 0xc4) {
- /* Three byte VEX prefix. */
- fetch_data(the_info, codep + 3);
- vex3 = codep[2];
-
- newrex |= (vex2 & 0x80 ? 0 : REX_R);
- newrex |= (vex2 & 0x40 ? 0 : REX_X);
- newrex |= (vex2 & 0x20 ? 0 : REX_B);
- newrex |= (vex3 & 0x80 ? REX_W : 0);
- switch (vex2 & 0x1f) { /* VEX.m-mmmm */
- case 1:
- newpfx |= PREFIX_VEX_0F;
- break;
- case 2:
- newpfx |= PREFIX_VEX_0F | PREFIX_VEX_0F38;
- break;
- case 3:
- newpfx |= PREFIX_VEX_0F | PREFIX_VEX_0F3A;
- break;
- }
- vex2 = vex3;
- codep += 3;
- } else {
- /* Two byte VEX prefix. */
- newrex |= (vex2 & 0x80 ? 0 : REX_R);
- newpfx |= PREFIX_VEX_0F;
- codep += 2;
- }
-
- vex_reg = (~vex2 >> 3) & 15; /* VEX.vvvv */
- switch (vex2 & 3) { /* VEX.pp */
- case 1:
- newpfx |= PREFIX_DATA; /* 0x66 */
- break;
- case 2:
- newpfx |= PREFIX_REPZ; /* 0xf3 */
- break;
- case 3:
- newpfx |= PREFIX_REPNZ; /* 0xf2 */
- break;
- }
-
- rex = newrex;
- prefixes = newpfx;
-}
-
-/* Return the name of the prefix byte PREF, or NULL if PREF is not a
- prefix byte. */
-
-static const char *
-prefix_name (int pref, int sizeflag)
-{
- static const char * const rexes [16] =
- {
- "rex", /* 0x40 */
- "rex.B", /* 0x41 */
- "rex.X", /* 0x42 */
- "rex.XB", /* 0x43 */
- "rex.R", /* 0x44 */
- "rex.RB", /* 0x45 */
- "rex.RX", /* 0x46 */
- "rex.RXB", /* 0x47 */
- "rex.W", /* 0x48 */
- "rex.WB", /* 0x49 */
- "rex.WX", /* 0x4a */
- "rex.WXB", /* 0x4b */
- "rex.WR", /* 0x4c */
- "rex.WRB", /* 0x4d */
- "rex.WRX", /* 0x4e */
- "rex.WRXB", /* 0x4f */
- };
-
- switch (pref)
- {
- /* REX prefixes family. */
- case 0x40:
- case 0x41:
- case 0x42:
- case 0x43:
- case 0x44:
- case 0x45:
- case 0x46:
- case 0x47:
- case 0x48:
- case 0x49:
- case 0x4a:
- case 0x4b:
- case 0x4c:
- case 0x4d:
- case 0x4e:
- case 0x4f:
- return rexes [pref - 0x40];
- case 0xf3:
- return "repz";
- case 0xf2:
- return "repnz";
- case 0xf0:
- return "lock";
- case 0x2e:
- return "cs";
- case 0x36:
- return "ss";
- case 0x3e:
- return "ds";
- case 0x26:
- return "es";
- case 0x64:
- return "fs";
- case 0x65:
- return "gs";
- case 0x66:
- return (sizeflag & DFLAG) ? "data16" : "data32";
- case 0x67:
- if (address_mode == mode_64bit)
- return (sizeflag & AFLAG) ? "addr32" : "addr64";
- else
- return (sizeflag & AFLAG) ? "addr16" : "addr32";
- case FWAIT_OPCODE:
- return "fwait";
- default:
- return NULL;
- }
-}
-
-static char op_out[MAX_OPERANDS][100];
-static int op_ad, op_index[MAX_OPERANDS];
-static int two_source_ops;
-static bfd_vma op_address[MAX_OPERANDS];
-static bfd_vma op_riprel[MAX_OPERANDS];
-static bfd_vma start_pc;
-
-/*
- * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
- * (see topic "Redundant prefixes" in the "Differences from 8086"
- * section of the "Virtual 8086 Mode" chapter.)
- * 'pc' should be the address of this instruction, it will
- * be used to print the target address if this is a relative jump or call
- * The function returns the length of this instruction in bytes.
- */
-
-static char intel_syntax;
-static char open_char;
-static char close_char;
-static char separator_char;
-static char scale_char;
-
-int
-print_insn_i386 (bfd_vma pc, disassemble_info *info)
-{
- intel_syntax = -1;
-
- return print_insn (pc, info);
-}
-
-static int
-print_insn (bfd_vma pc, disassemble_info *info)
-{
- const struct dis386 *dp;
- int i;
- char *op_txt[MAX_OPERANDS];
- int needcomma;
- unsigned char uses_DATA_prefix, uses_LOCK_prefix;
- unsigned char uses_REPNZ_prefix, uses_REPZ_prefix;
- int sizeflag;
- const char *p;
- struct dis_private priv;
- unsigned char op;
- unsigned char threebyte;
-
- if (info->mach == bfd_mach_x86_64_intel_syntax
- || info->mach == bfd_mach_x86_64)
- address_mode = mode_64bit;
- else
- address_mode = mode_32bit;
-
- if (intel_syntax == (char) -1)
- intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
- || info->mach == bfd_mach_x86_64_intel_syntax);
-
- if (info->mach == bfd_mach_i386_i386
- || info->mach == bfd_mach_x86_64
- || info->mach == bfd_mach_i386_i386_intel_syntax
- || info->mach == bfd_mach_x86_64_intel_syntax)
- priv.orig_sizeflag = AFLAG | DFLAG;
- else if (info->mach == bfd_mach_i386_i8086)
- priv.orig_sizeflag = 0;
- else
- abort ();
-
- for (p = info->disassembler_options; p != NULL; )
- {
- if (strncmp (p, "x86-64", 6) == 0)
- {
- address_mode = mode_64bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
- }
- else if (strncmp (p, "i386", 4) == 0)
- {
- address_mode = mode_32bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
- }
- else if (strncmp (p, "i8086", 5) == 0)
- {
- address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
- }
- else if (strncmp (p, "intel", 5) == 0)
- {
- intel_syntax = 1;
- }
- else if (strncmp (p, "att", 3) == 0)
- {
- intel_syntax = 0;
- }
- else if (strncmp (p, "addr", 4) == 0)
- {
- if (address_mode == mode_64bit)
- {
- if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag &= ~AFLAG;
- else if (p[4] == '6' && p[5] == '4')
- priv.orig_sizeflag |= AFLAG;
- }
- else
- {
- if (p[4] == '1' && p[5] == '6')
- priv.orig_sizeflag &= ~AFLAG;
- else if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag |= AFLAG;
- }
- }
- else if (strncmp (p, "data", 4) == 0)
- {
- if (p[4] == '1' && p[5] == '6')
- priv.orig_sizeflag &= ~DFLAG;
- else if (p[4] == '3' && p[5] == '2')
- priv.orig_sizeflag |= DFLAG;
- }
- else if (strncmp (p, "suffix", 6) == 0)
- priv.orig_sizeflag |= SUFFIX_ALWAYS;
-
- p = strchr (p, ',');
- if (p != NULL)
- p++;
- }
-
- if (intel_syntax)
- {
- names64 = intel_names64;
- names32 = intel_names32;
- names16 = intel_names16;
- names8 = intel_names8;
- names8rex = intel_names8rex;
- names_seg = intel_names_seg;
- index16 = intel_index16;
- open_char = '[';
- close_char = ']';
- separator_char = '+';
- scale_char = '*';
- }
- else
- {
- names64 = att_names64;
- names32 = att_names32;
- names16 = att_names16;
- names8 = att_names8;
- names8rex = att_names8rex;
- names_seg = att_names_seg;
- index16 = att_index16;
- open_char = '(';
- close_char = ')';
- separator_char = ',';
- scale_char = ',';
- }
-
- /* The output looks better if we put 7 bytes on a line, since that
- puts most long word instructions on a single line. */
- info->bytes_per_line = 7;
-
- info->private_data = &priv;
- priv.max_fetched = priv.the_buffer;
- priv.insn_start = pc;
-
- obuf[0] = 0;
- for (i = 0; i < MAX_OPERANDS; ++i)
- {
- op_out[i][0] = 0;
- op_index[i] = -1;
- }
-
- the_info = info;
- start_pc = pc;
- start_codep = priv.the_buffer;
- codep = priv.the_buffer;
-
- if (sigsetjmp(priv.bailout, 0) != 0)
- {
- const char *name;
-
- /* Getting here means we tried for data but didn't get it. That
- means we have an incomplete instruction of some sort. Just
- print the first byte as a prefix or a .byte pseudo-op. */
- if (codep > priv.the_buffer)
- {
- name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
- if (name != NULL)
- (*info->fprintf_func) (info->stream, "%s", name);
- else
- {
- /* Just print the first byte as a .byte instruction. */
- (*info->fprintf_func) (info->stream, ".byte 0x%x",
- (unsigned int) priv.the_buffer[0]);
- }
-
- return 1;
- }
-
- return -1;
- }
-
- obufp = obuf;
- ckprefix ();
- ckvexprefix ();
-
- insn_codep = codep;
- sizeflag = priv.orig_sizeflag;
-
- fetch_data(info, codep + 1);
- two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
-
- if (((prefixes & PREFIX_FWAIT)
- && ((*codep < 0xd8) || (*codep > 0xdf)))
- || (rex && rex_used))
- {
- const char *name;
-
- /* fwait not followed by floating point instruction, or rex followed
- by other prefixes. Print the first prefix. */
- name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
- if (name == NULL)
- name = INTERNAL_DISASSEMBLER_ERROR;
- (*info->fprintf_func) (info->stream, "%s", name);
- return 1;
- }
-
- op = 0;
- if (prefixes & PREFIX_VEX_0F)
- {
- used_prefixes |= PREFIX_VEX_0F | PREFIX_VEX_0F38 | PREFIX_VEX_0F3A;
- if (prefixes & PREFIX_VEX_0F38)
- threebyte = 0x38;
- else if (prefixes & PREFIX_VEX_0F3A)
- threebyte = 0x3a;
- else
- threebyte = *codep++;
- goto vex_opcode;
- }
- if (*codep == 0x0f)
- {
- fetch_data(info, codep + 2);
- threebyte = codep[1];
- codep += 2;
- vex_opcode:
- dp = &dis386_twobyte[threebyte];
- need_modrm = twobyte_has_modrm[threebyte];
- uses_DATA_prefix = twobyte_uses_DATA_prefix[threebyte];
- uses_REPNZ_prefix = twobyte_uses_REPNZ_prefix[threebyte];
- uses_REPZ_prefix = twobyte_uses_REPZ_prefix[threebyte];
- uses_LOCK_prefix = (threebyte & ~0x02) == 0x20;
- if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE)
- {
- fetch_data(info, codep + 2);
- op = *codep++;
- switch (threebyte)
- {
- case 0x38:
- uses_DATA_prefix = threebyte_0x38_uses_DATA_prefix[op];
- uses_REPNZ_prefix = threebyte_0x38_uses_REPNZ_prefix[op];
- uses_REPZ_prefix = threebyte_0x38_uses_REPZ_prefix[op];
- break;
- case 0x3a:
- uses_DATA_prefix = threebyte_0x3a_uses_DATA_prefix[op];
- uses_REPNZ_prefix = threebyte_0x3a_uses_REPNZ_prefix[op];
- uses_REPZ_prefix = threebyte_0x3a_uses_REPZ_prefix[op];
- break;
- default:
- break;
- }
- }
- }
- else
- {
- dp = &dis386[*codep];
- need_modrm = onebyte_has_modrm[*codep];
- uses_DATA_prefix = 0;
- uses_REPNZ_prefix = 0;
- /* pause is 0xf3 0x90. */
- uses_REPZ_prefix = *codep == 0x90;
- uses_LOCK_prefix = 0;
- codep++;
- }
-
- if (!uses_REPZ_prefix && (prefixes & PREFIX_REPZ))
- {
- oappend ("repz ");
- used_prefixes |= PREFIX_REPZ;
- }
- if (!uses_REPNZ_prefix && (prefixes & PREFIX_REPNZ))
- {
- oappend ("repnz ");
- used_prefixes |= PREFIX_REPNZ;
- }
-
- if (!uses_LOCK_prefix && (prefixes & PREFIX_LOCK))
- {
- oappend ("lock ");
- used_prefixes |= PREFIX_LOCK;
- }
-
- if (prefixes & PREFIX_ADDR)
- {
- sizeflag ^= AFLAG;
- if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
- {
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- oappend ("addr32 ");
- else
- oappend ("addr16 ");
- used_prefixes |= PREFIX_ADDR;
- }
- }
-
- if (!uses_DATA_prefix && (prefixes & PREFIX_DATA))
- {
- sizeflag ^= DFLAG;
- if (dp->op[2].bytemode == cond_jump_mode
- && dp->op[0].bytemode == v_mode
- && !intel_syntax)
- {
- if (sizeflag & DFLAG)
- oappend ("data32 ");
- else
- oappend ("data16 ");
- used_prefixes |= PREFIX_DATA;
- }
- }
-
- if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE)
- {
- dp = &three_byte_table[dp->op[1].bytemode][op];
- modrm.mod = (*codep >> 6) & 3;
- modrm.reg = (*codep >> 3) & 7;
- modrm.rm = *codep & 7;
- }
- else if (need_modrm)
- {
- fetch_data(info, codep + 1);
- modrm.mod = (*codep >> 6) & 3;
- modrm.reg = (*codep >> 3) & 7;
- modrm.rm = *codep & 7;
- }
-
- if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
- {
- dofloat (sizeflag);
- }
- else
- {
- int index;
- if (dp->name == NULL)
- {
- switch (dp->op[0].bytemode)
- {
- case USE_GROUPS:
- dp = &grps[dp->op[1].bytemode][modrm.reg];
- break;
-
- case USE_PREFIX_USER_TABLE:
- index = 0;
- used_prefixes |= (prefixes & PREFIX_REPZ);
- if (prefixes & PREFIX_REPZ)
- index = 1;
- else
- {
- /* We should check PREFIX_REPNZ and PREFIX_REPZ
- before PREFIX_DATA. */
- used_prefixes |= (prefixes & PREFIX_REPNZ);
- if (prefixes & PREFIX_REPNZ)
- index = 3;
- else
- {
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- index = 2;
- }
- }
- dp = &prefix_user_table[dp->op[1].bytemode][index];
- break;
-
- case X86_64_SPECIAL:
- index = address_mode == mode_64bit ? 1 : 0;
- dp = &x86_64_table[dp->op[1].bytemode][index];
- break;
-
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
- }
-
- if (dp->name != NULL && putop (dp->name, sizeflag) == 0)
- {
- for (i = 0; i < MAX_OPERANDS; ++i)
- {
- obufp = op_out[i];
- op_ad = MAX_OPERANDS - 1 - i;
- if (dp->op[i].rtn)
- (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
- }
- }
- }
-
- /* See if any prefixes were not used. If so, print the first one
- separately. If we don't do this, we'll wind up printing an
- instruction stream which does not precisely correspond to the
- bytes we are disassembling. */
- if ((prefixes & ~used_prefixes) != 0)
- {
- const char *name;
-
- name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
- if (name == NULL)
- name = INTERNAL_DISASSEMBLER_ERROR;
- (*info->fprintf_func) (info->stream, "%s", name);
- return 1;
- }
- if (rex & ~rex_used)
- {
- const char *name;
- name = prefix_name (rex | 0x40, priv.orig_sizeflag);
- if (name == NULL)
- name = INTERNAL_DISASSEMBLER_ERROR;
- (*info->fprintf_func) (info->stream, "%s ", name);
- }
-
- obufp = obuf + strlen (obuf);
- for (i = strlen (obuf); i < 6; i++)
- oappend (" ");
- oappend (" ");
- (*info->fprintf_func) (info->stream, "%s", obuf);
-
- /* The enter and bound instructions are printed with operands in the same
- order as the intel book; everything else is printed in reverse order. */
- if (intel_syntax || two_source_ops)
- {
- bfd_vma riprel;
-
- for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[i] = op_out[i];
-
- for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
- {
- op_ad = op_index[i];
- op_index[i] = op_index[MAX_OPERANDS - 1 - i];
- op_index[MAX_OPERANDS - 1 - i] = op_ad;
- riprel = op_riprel[i];
- op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
- op_riprel[MAX_OPERANDS - 1 - i] = riprel;
- }
- }
- else
- {
- for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
- }
-
- needcomma = 0;
- for (i = 0; i < MAX_OPERANDS; ++i)
- if (*op_txt[i])
- {
- if (needcomma)
- (*info->fprintf_func) (info->stream, ",");
- if (op_index[i] != -1 && !op_riprel[i])
- (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
- else
- (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
- needcomma = 1;
- }
-
- for (i = 0; i < MAX_OPERANDS; i++)
- if (op_index[i] != -1 && op_riprel[i])
- {
- (*info->fprintf_func) (info->stream, " # ");
- (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
- + op_address[op_index[i]]), info);
- break;
- }
- return codep - priv.the_buffer;
-}
-
-static const char *float_mem[] = {
- /* d8 */
- "fadd{s||s|}",
- "fmul{s||s|}",
- "fcom{s||s|}",
- "fcomp{s||s|}",
- "fsub{s||s|}",
- "fsubr{s||s|}",
- "fdiv{s||s|}",
- "fdivr{s||s|}",
- /* d9 */
- "fld{s||s|}",
- "(bad)",
- "fst{s||s|}",
- "fstp{s||s|}",
- "fldenvIC",
- "fldcw",
- "fNstenvIC",
- "fNstcw",
- /* da */
- "fiadd{l||l|}",
- "fimul{l||l|}",
- "ficom{l||l|}",
- "ficomp{l||l|}",
- "fisub{l||l|}",
- "fisubr{l||l|}",
- "fidiv{l||l|}",
- "fidivr{l||l|}",
- /* db */
- "fild{l||l|}",
- "fisttp{l||l|}",
- "fist{l||l|}",
- "fistp{l||l|}",
- "(bad)",
- "fld{t||t|}",
- "(bad)",
- "fstp{t||t|}",
- /* dc */
- "fadd{l||l|}",
- "fmul{l||l|}",
- "fcom{l||l|}",
- "fcomp{l||l|}",
- "fsub{l||l|}",
- "fsubr{l||l|}",
- "fdiv{l||l|}",
- "fdivr{l||l|}",
- /* dd */
- "fld{l||l|}",
- "fisttp{ll||ll|}",
- "fst{l||l|}",
- "fstp{l||l|}",
- "frstorIC",
- "(bad)",
- "fNsaveIC",
- "fNstsw",
- /* de */
- "fiadd",
- "fimul",
- "ficom",
- "ficomp",
- "fisub",
- "fisubr",
- "fidiv",
- "fidivr",
- /* df */
- "fild",
- "fisttp",
- "fist",
- "fistp",
- "fbld",
- "fild{ll||ll|}",
- "fbstp",
- "fistp{ll||ll|}",
-};
-
-static const unsigned char float_mem_mode[] = {
- /* d8 */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- /* d9 */
- d_mode,
- 0,
- d_mode,
- d_mode,
- 0,
- w_mode,
- 0,
- w_mode,
- /* da */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- /* db */
- d_mode,
- d_mode,
- d_mode,
- d_mode,
- 0,
- t_mode,
- 0,
- t_mode,
- /* dc */
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- /* dd */
- q_mode,
- q_mode,
- q_mode,
- q_mode,
- 0,
- 0,
- 0,
- w_mode,
- /* de */
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- /* df */
- w_mode,
- w_mode,
- w_mode,
- w_mode,
- t_mode,
- q_mode,
- t_mode,
- q_mode
-};
-
-#define ST { OP_ST, 0 }
-#define STi { OP_STi, 0 }
-
-#define FGRPd9_2 NULL, { { NULL, 0 } }
-#define FGRPd9_4 NULL, { { NULL, 1 } }
-#define FGRPd9_5 NULL, { { NULL, 2 } }
-#define FGRPd9_6 NULL, { { NULL, 3 } }
-#define FGRPd9_7 NULL, { { NULL, 4 } }
-#define FGRPda_5 NULL, { { NULL, 5 } }
-#define FGRPdb_4 NULL, { { NULL, 6 } }
-#define FGRPde_3 NULL, { { NULL, 7 } }
-#define FGRPdf_4 NULL, { { NULL, 8 } }
-
-static const struct dis386 float_reg[][8] = {
- /* d8 */
- {
- { "fadd", { ST, STi } },
- { "fmul", { ST, STi } },
- { "fcom", { STi } },
- { "fcomp", { STi } },
- { "fsub", { ST, STi } },
- { "fsubr", { ST, STi } },
- { "fdiv", { ST, STi } },
- { "fdivr", { ST, STi } },
- },
- /* d9 */
- {
- { "fld", { STi } },
- { "fxch", { STi } },
- { FGRPd9_2 },
- { "(bad)", { XX } },
- { FGRPd9_4 },
- { FGRPd9_5 },
- { FGRPd9_6 },
- { FGRPd9_7 },
- },
- /* da */
- {
- { "fcmovb", { ST, STi } },
- { "fcmove", { ST, STi } },
- { "fcmovbe",{ ST, STi } },
- { "fcmovu", { ST, STi } },
- { "(bad)", { XX } },
- { FGRPda_5 },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* db */
- {
- { "fcmovnb",{ ST, STi } },
- { "fcmovne",{ ST, STi } },
- { "fcmovnbe",{ ST, STi } },
- { "fcmovnu",{ ST, STi } },
- { FGRPdb_4 },
- { "fucomi", { ST, STi } },
- { "fcomi", { ST, STi } },
- { "(bad)", { XX } },
- },
- /* dc */
- {
- { "fadd", { STi, ST } },
- { "fmul", { STi, ST } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
-#if SYSV386_COMPAT
- { "fsub", { STi, ST } },
- { "fsubr", { STi, ST } },
- { "fdiv", { STi, ST } },
- { "fdivr", { STi, ST } },
-#else
- { "fsubr", { STi, ST } },
- { "fsub", { STi, ST } },
- { "fdivr", { STi, ST } },
- { "fdiv", { STi, ST } },
-#endif
- },
- /* dd */
- {
- { "ffree", { STi } },
- { "(bad)", { XX } },
- { "fst", { STi } },
- { "fstp", { STi } },
- { "fucom", { STi } },
- { "fucomp", { STi } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- },
- /* de */
- {
- { "faddp", { STi, ST } },
- { "fmulp", { STi, ST } },
- { "(bad)", { XX } },
- { FGRPde_3 },
-#if SYSV386_COMPAT
- { "fsubp", { STi, ST } },
- { "fsubrp", { STi, ST } },
- { "fdivp", { STi, ST } },
- { "fdivrp", { STi, ST } },
-#else
- { "fsubrp", { STi, ST } },
- { "fsubp", { STi, ST } },
- { "fdivrp", { STi, ST } },
- { "fdivp", { STi, ST } },
-#endif
- },
- /* df */
- {
- { "ffreep", { STi } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { FGRPdf_4 },
- { "fucomip", { ST, STi } },
- { "fcomip", { ST, STi } },
- { "(bad)", { XX } },
- },
-};
-
-static const char *fgrps[][8] = {
- /* d9_2 0 */
- {
- "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
-
- /* d9_4 1 */
- {
- "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
- },
-
- /* d9_5 2 */
- {
- "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
- },
-
- /* d9_6 3 */
- {
- "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
- },
-
- /* d9_7 4 */
- {
- "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
- },
-
- /* da_5 5 */
- {
- "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
-
- /* db_4 6 */
- {
- "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
- "fNsetpm(287 only)","(bad)","(bad)","(bad)",
- },
-
- /* de_3 7 */
- {
- "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
-
- /* df_4 8 */
- {
- "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
- },
-};
-
-static void
-dofloat (int sizeflag)
-{
- const struct dis386 *dp;
- unsigned char floatop;
-
- floatop = codep[-1];
-
- if (modrm.mod != 3)
- {
- int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
-
- putop (float_mem[fp_indx], sizeflag);
- obufp = op_out[0];
- op_ad = 2;
- OP_E (float_mem_mode[fp_indx], sizeflag);
- return;
- }
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- dp = &float_reg[floatop - 0xd8][modrm.reg];
- if (dp->name == NULL)
- {
- putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
-
- /* Instruction fnstsw is only one with strange arg. */
- if (floatop == 0xdf && codep[-1] == 0xe0)
- pstrcpy (op_out[0], sizeof(op_out[0]), names16[0]);
- }
- else
- {
- putop (dp->name, sizeflag);
-
- obufp = op_out[0];
- op_ad = 2;
- if (dp->op[0].rtn)
- (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
-
- obufp = op_out[1];
- op_ad = 1;
- if (dp->op[1].rtn)
- (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
- }
-}
-
-static void
-OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- oappend ("%st" + intel_syntax);
-}
-
-static void
-OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- snprintf (scratchbuf, sizeof(scratchbuf), "%%st(%d)", modrm.rm);
- oappend (scratchbuf + intel_syntax);
-}
-
-/* Capital letters in template are macros. */
-static int
-putop (const char *template, int sizeflag)
-{
- const char *p;
- int alt = 0;
-
- for (p = template; *p; p++)
- {
- switch (*p)
- {
- default:
- *obufp++ = *p;
- break;
- case '{':
- alt = 0;
- if (intel_syntax)
- alt += 1;
- if (address_mode == mode_64bit)
- alt += 2;
- while (alt != 0)
- {
- while (*++p != '|')
- {
- if (*p == '}')
- {
- /* Alternative not valid. */
- pstrcpy (obuf, sizeof(obuf), "(bad)");
- obufp = obuf + 5;
- return 1;
- }
- else if (*p == '\0')
- abort ();
- }
- alt--;
- }
- /* Fall through. */
- case 'I':
- alt = 1;
- continue;
- case '|':
- while (*++p != '}')
- {
- if (*p == '\0')
- abort ();
- }
- break;
- case '}':
- break;
- case 'A':
- if (intel_syntax)
- break;
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- *obufp++ = 'b';
- break;
- case 'B':
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'b';
- break;
- case 'C':
- if (intel_syntax && !alt)
- break;
- if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = intel_syntax ? 'w' : 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case 'D':
- if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
- break;
- USED_REX (REX_W);
- if (modrm.mod == 3)
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- else
- *obufp++ = 'w';
- break;
- case 'E': /* For jcxz/jecxz */
- if (address_mode == mode_64bit)
- {
- if (sizeflag & AFLAG)
- *obufp++ = 'r';
- else
- *obufp++ = 'e';
- }
- else
- if (sizeflag & AFLAG)
- *obufp++ = 'e';
- used_prefixes |= (prefixes & PREFIX_ADDR);
- break;
- case 'F':
- if (intel_syntax)
- break;
- if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
- {
- if (sizeflag & AFLAG)
- *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
- else
- *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
- used_prefixes |= (prefixes & PREFIX_ADDR);
- }
- break;
- case 'G':
- if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- if ((rex & REX_W) || (sizeflag & DFLAG))
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'H':
- if (intel_syntax)
- break;
- if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
- || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
- {
- used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
- *obufp++ = ',';
- *obufp++ = 'p';
- if (prefixes & PREFIX_DS)
- *obufp++ = 't';
- else
- *obufp++ = 'n';
- }
- break;
- case 'J':
- if (intel_syntax)
- break;
- *obufp++ = 'l';
- break;
- case 'K':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- *obufp++ = 'd';
- break;
- case 'Z':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'L':
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'l';
- break;
- case 'N':
- if ((prefixes & PREFIX_FWAIT) == 0)
- *obufp++ = 'n';
- else
- used_prefixes |= PREFIX_FWAIT;
- break;
- case 'O':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'o';
- else if (intel_syntax && (sizeflag & DFLAG))
- *obufp++ = 'q';
- else
- *obufp++ = 'd';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'T':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'P':
- if (intel_syntax)
- break;
- if ((prefixes & PREFIX_DATA)
- || (rex & REX_W)
- || (sizeflag & SUFFIX_ALWAYS))
- {
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case 'U':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'Q':
- if (intel_syntax && !alt)
- break;
- USED_REX (REX_W);
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = intel_syntax ? 'd' : 'l';
- else
- *obufp++ = 'w';
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case 'R':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else if (sizeflag & DFLAG)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
- }
- else
- *obufp++ = 'w';
- if (intel_syntax && !p[1]
- && ((rex & REX_W) || (sizeflag & DFLAG)))
- *obufp++ = 'e';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'V':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'S':
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- {
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- }
- break;
- case 'X':
- if (prefixes & PREFIX_DATA)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 'Y':
- if (intel_syntax)
- break;
- if (rex & REX_W)
- {
- USED_REX (REX_W);
- *obufp++ = 'q';
- }
- break;
- /* implicit operand size 'l' for i386 or 'q' for x86-64 */
- case 'W':
- /* operand size flag for cwtl, cbtw */
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
- }
- else if (sizeflag & DFLAG)
- *obufp++ = 'w';
- else
- *obufp++ = 'b';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- }
- alt = 0;
- }
- *obufp = 0;
- return 0;
-}
-
-static void
-oappend (const char *s)
-{
- strcpy (obufp, s);
- obufp += strlen (s);
-}
-
-static void
-append_seg (void)
-{
- if (prefixes & PREFIX_CS)
- {
- used_prefixes |= PREFIX_CS;
- oappend ("%cs:" + intel_syntax);
- }
- if (prefixes & PREFIX_DS)
- {
- used_prefixes |= PREFIX_DS;
- oappend ("%ds:" + intel_syntax);
- }
- if (prefixes & PREFIX_SS)
- {
- used_prefixes |= PREFIX_SS;
- oappend ("%ss:" + intel_syntax);
- }
- if (prefixes & PREFIX_ES)
- {
- used_prefixes |= PREFIX_ES;
- oappend ("%es:" + intel_syntax);
- }
- if (prefixes & PREFIX_FS)
- {
- used_prefixes |= PREFIX_FS;
- oappend ("%fs:" + intel_syntax);
- }
- if (prefixes & PREFIX_GS)
- {
- used_prefixes |= PREFIX_GS;
- oappend ("%gs:" + intel_syntax);
- }
-}
-
-static void
-OP_indirE (int bytemode, int sizeflag)
-{
- if (!intel_syntax)
- oappend ("*");
- OP_E (bytemode, sizeflag);
-}
-
-static void
-print_operand_value (char *buf, size_t bufsize, int hex, bfd_vma disp)
-{
- if (address_mode == mode_64bit)
- {
- if (hex)
- {
- char tmp[30];
- int i;
- buf[0] = '0';
- buf[1] = 'x';
- snprintf_vma (tmp, sizeof(tmp), disp);
- for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++) {
- }
- pstrcpy (buf + 2, bufsize - 2, tmp + i);
- }
- else
- {
- bfd_signed_vma v = disp;
- char tmp[30];
- int i;
- if (v < 0)
- {
- *(buf++) = '-';
- v = -disp;
- /* Check for possible overflow on 0x8000000000000000. */
- if (v < 0)
- {
- pstrcpy (buf, bufsize, "9223372036854775808");
- return;
- }
- }
- if (!v)
- {
- pstrcpy (buf, bufsize, "0");
- return;
- }
-
- i = 0;
- tmp[29] = 0;
- while (v)
- {
- tmp[28 - i] = (v % 10) + '0';
- v /= 10;
- i++;
- }
- pstrcpy (buf, bufsize, tmp + 29 - i);
- }
- }
- else
- {
- if (hex)
- snprintf (buf, bufsize, "0x%x", (unsigned int) disp);
- else
- snprintf (buf, bufsize, "%d", (int) disp);
- }
-}
-
-/* Put DISP in BUF as signed hex number. */
-
-static void
-print_displacement (char *buf, bfd_vma disp)
-{
- bfd_signed_vma val = disp;
- char tmp[30];
- int i, j = 0;
-
- if (val < 0)
- {
- buf[j++] = '-';
- val = -disp;
-
- /* Check for possible overflow. */
- if (val < 0)
- {
- switch (address_mode)
- {
- case mode_64bit:
- strcpy (buf + j, "0x8000000000000000");
- break;
- case mode_32bit:
- strcpy (buf + j, "0x80000000");
- break;
- case mode_16bit:
- strcpy (buf + j, "0x8000");
- break;
- }
- return;
- }
- }
-
- buf[j++] = '0';
- buf[j++] = 'x';
-
- snprintf_vma (tmp, sizeof(tmp), val);
- for (i = 0; tmp[i] == '0'; i++)
- continue;
- if (tmp[i] == '\0')
- i--;
- strcpy (buf + j, tmp + i);
-}
-
-static void
-intel_operand_size (int bytemode, int sizeflag)
-{
- switch (bytemode)
- {
- case b_mode:
- case dqb_mode:
- oappend ("BYTE PTR ");
- break;
- case w_mode:
- case dqw_mode:
- oappend ("WORD PTR ");
- break;
- case stack_v_mode:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- oappend ("QWORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- }
- /* FALLTHRU */
- case v_mode:
- case dq_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend ("QWORD PTR ");
- else if ((sizeflag & DFLAG) || bytemode == dq_mode)
- oappend ("DWORD PTR ");
- else
- oappend ("WORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case z_mode:
- if ((rex & REX_W) || (sizeflag & DFLAG))
- *obufp++ = 'D';
- oappend ("WORD PTR ");
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case d_mode:
- case dqd_mode:
- oappend ("DWORD PTR ");
- break;
- case q_mode:
- oappend ("QWORD PTR ");
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend ("QWORD PTR ");
- else
- oappend ("DWORD PTR ");
- break;
- case f_mode:
- if (sizeflag & DFLAG)
- oappend ("FWORD PTR ");
- else
- oappend ("DWORD PTR ");
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case t_mode:
- oappend ("TBYTE PTR ");
- break;
- case x_mode:
- oappend ("XMMWORD PTR ");
- break;
- case o_mode:
- oappend ("OWORD PTR ");
- break;
- default:
- break;
- }
-}
-
-static void
-OP_E (int bytemode, int sizeflag)
-{
- bfd_vma disp;
- int add = 0;
- int riprel = 0;
- USED_REX (REX_B);
- if (rex & REX_B)
- add += 8;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (modrm.mod == 3)
- {
- switch (bytemode)
- {
- case b_mode:
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.rm + add]);
- else
- oappend (names8[modrm.rm + add]);
- break;
- case w_mode:
- oappend (names16[modrm.rm + add]);
- break;
- case d_mode:
- oappend (names32[modrm.rm + add]);
- break;
- case q_mode:
- oappend (names64[modrm.rm + add]);
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend (names64[modrm.rm + add]);
- else
- oappend (names32[modrm.rm + add]);
- break;
- case stack_v_mode:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- oappend (names64[modrm.rm + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- }
- bytemode = v_mode;
- /* FALLTHRU */
- case v_mode:
- case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.rm + add]);
- else if ((sizeflag & DFLAG) || bytemode != v_mode)
- oappend (names32[modrm.rm + add]);
- else
- oappend (names16[modrm.rm + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case 0:
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
- return;
- }
-
- disp = 0;
- if (intel_syntax)
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
-
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int havedisp;
- int havesib;
- int havebase;
- int base;
- int index = 0;
- int scale = 0;
-
- havesib = 0;
- havebase = 1;
- base = modrm.rm;
-
- if (base == 4)
- {
- havesib = 1;
- fetch_data(the_info, codep + 1);
- index = (*codep >> 3) & 7;
- if (address_mode == mode_64bit || index != 0x4)
- /* When INDEX == 0x4 in 32 bit mode, SCALE is ignored. */
- scale = (*codep >> 6) & 3;
- base = *codep & 7;
- USED_REX (REX_X);
- if (rex & REX_X)
- index += 8;
- codep++;
- }
- base += add;
-
- switch (modrm.mod)
- {
- case 0:
- if ((base & 7) == 5)
- {
- havebase = 0;
- if (address_mode == mode_64bit && !havesib)
- riprel = 1;
- disp = get32s ();
- }
- break;
- case 1:
- fetch_data (the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
- break;
- case 2:
- disp = get32s ();
- break;
- }
-
- havedisp = havebase || (havesib && (index != 4 || scale != 0));
-
- if (!intel_syntax)
- if (modrm.mod != 0 || (base & 7) == 5)
- {
- if (havedisp || riprel)
- print_displacement (scratchbuf, disp);
- else
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1, disp);
- oappend (scratchbuf);
- if (riprel)
- {
- set_op (disp, 1);
- oappend ("(%rip)");
- }
- }
-
- if (havedisp || (intel_syntax && riprel))
- {
- *obufp++ = open_char;
- if (intel_syntax && riprel)
- {
- set_op (disp, 1);
- oappend ("rip");
- }
- *obufp = '\0';
- if (havebase)
- oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
- ? names64[base] : names32[base]);
- if (havesib)
- {
- if (index != 4)
- {
- if (!intel_syntax || havebase)
- {
- *obufp++ = separator_char;
- *obufp = '\0';
- }
- oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
- ? names64[index] : names32[index]);
- }
- if (scale != 0 || (!intel_syntax && index != 4))
- {
- *obufp++ = scale_char;
- *obufp = '\0';
- snprintf (scratchbuf, sizeof(scratchbuf), "%d", 1 << scale);
- oappend (scratchbuf);
- }
- }
- if (intel_syntax
- && (disp || modrm.mod != 0 || (base & 7) == 5))
- {
- if ((bfd_signed_vma) disp >= 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
- else if (modrm.mod != 1)
- {
- *obufp++ = '-';
- *obufp = '\0';
- disp = - (bfd_signed_vma) disp;
- }
-
- print_displacement (scratchbuf, disp);
- oappend (scratchbuf);
- }
-
- *obufp++ = close_char;
- *obufp = '\0';
- }
- else if (intel_syntax)
- {
- if (modrm.mod != 0 || (base & 7) == 5)
- {
- if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS))
- ;
- else
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1, disp);
- oappend (scratchbuf);
- }
- }
- }
- else
- { /* 16 bit address mode */
- switch (modrm.mod)
- {
- case 0:
- if (modrm.rm == 6)
- {
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
- }
- break;
- case 1:
- fetch_data(the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
- break;
- case 2:
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
- break;
- }
-
- if (!intel_syntax)
- if (modrm.mod != 0 || modrm.rm == 6)
- {
- print_displacement (scratchbuf, disp);
- oappend (scratchbuf);
- }
-
- if (modrm.mod != 0 || modrm.rm != 6)
- {
- *obufp++ = open_char;
- *obufp = '\0';
- oappend (index16[modrm.rm]);
- if (intel_syntax
- && (disp || modrm.mod != 0 || modrm.rm == 6))
- {
- if ((bfd_signed_vma) disp >= 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
- else if (modrm.mod != 1)
- {
- *obufp++ = '-';
- *obufp = '\0';
- disp = - (bfd_signed_vma) disp;
- }
-
- print_displacement (scratchbuf, disp);
- oappend (scratchbuf);
- }
-
- *obufp++ = close_char;
- *obufp = '\0';
- }
- else if (intel_syntax)
- {
- if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS))
- ;
- else
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1,
- disp & 0xffff);
- oappend (scratchbuf);
- }
- }
-}
-
-static void
-OP_G (int bytemode, int sizeflag)
-{
- int add = 0;
- USED_REX (REX_R);
- if (rex & REX_R)
- add += 8;
- switch (bytemode)
- {
- case b_mode:
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.reg + add]);
- else
- oappend (names8[modrm.reg + add]);
- break;
- case w_mode:
- oappend (names16[modrm.reg + add]);
- break;
- case d_mode:
- oappend (names32[modrm.reg + add]);
- break;
- case q_mode:
- oappend (names64[modrm.reg + add]);
- break;
- case v_mode:
- case dq_mode:
- case dqb_mode:
- case dqd_mode:
- case dqw_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.reg + add]);
- else if ((sizeflag & DFLAG) || bytemode != v_mode)
- oappend (names32[modrm.reg + add]);
- else
- oappend (names16[modrm.reg + add]);
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case m_mode:
- if (address_mode == mode_64bit)
- oappend (names64[modrm.reg + add]);
- else
- oappend (names32[modrm.reg + add]);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
-}
-
-static void
-OP_vvvv (int bytemode, int sizeflags)
-{
- USED_REX (REX_W);
- if (rex & REX_W) {
- oappend(names64[vex_reg]);
- } else {
- oappend(names32[vex_reg]);
- }
-}
-
-static bfd_vma
-get64 (void)
-{
- bfd_vma x;
-#ifdef BFD64
- unsigned int a;
- unsigned int b;
-
- fetch_data(the_info, codep + 8);
- a = *codep++ & 0xff;
- a |= (*codep++ & 0xff) << 8;
- a |= (*codep++ & 0xff) << 16;
- a |= (*codep++ & 0xff) << 24;
- b = *codep++ & 0xff;
- b |= (*codep++ & 0xff) << 8;
- b |= (*codep++ & 0xff) << 16;
- b |= (*codep++ & 0xff) << 24;
- x = a + ((bfd_vma) b << 32);
-#else
- abort ();
- x = 0;
-#endif
- return x;
-}
-
-static bfd_signed_vma
-get32 (void)
-{
- bfd_signed_vma x = 0;
-
- fetch_data(the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
- return x;
-}
-
-static bfd_signed_vma
-get32s (void)
-{
- bfd_signed_vma x = 0;
-
- fetch_data(the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
-
- x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
-
- return x;
-}
-
-static int
-get16 (void)
-{
- int x = 0;
-
- fetch_data(the_info, codep + 2);
- x = *codep++ & 0xff;
- x |= (*codep++ & 0xff) << 8;
- return x;
-}
-
-static void
-set_op (bfd_vma op, int riprel)
-{
- op_index[op_ad] = op_ad;
- if (address_mode == mode_64bit)
- {
- op_address[op_ad] = op;
- op_riprel[op_ad] = riprel;
- }
- else
- {
- /* Mask to get a 32-bit address. */
- op_address[op_ad] = op & 0xffffffff;
- op_riprel[op_ad] = riprel & 0xffffffff;
- }
-}
-
-static void
-OP_REG (int code, int sizeflag)
-{
- const char *s;
- int add = 0;
- USED_REX (REX_B);
- if (rex & REX_B)
- add = 8;
-
- switch (code)
- {
- case ax_reg: case cx_reg: case dx_reg: case bx_reg:
- case sp_reg: case bp_reg: case si_reg: case di_reg:
- s = names16[code - ax_reg + add];
- break;
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- s = names_seg[code - es_reg + add];
- break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
- USED_REX (0);
- if (rex)
- s = names8rex[code - al_reg + add];
- else
- s = names8[code - al_reg];
- break;
- case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
- case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
- {
- s = names64[code - rAX_reg + add];
- break;
- }
- code += eAX_reg - rAX_reg;
- /* Fall through. */
- case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
- case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
- USED_REX (REX_W);
- if (rex & REX_W)
- s = names64[code - eAX_reg + add];
- else if (sizeflag & DFLAG)
- s = names32[code - eAX_reg + add];
- else
- s = names16[code - eAX_reg + add];
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- default:
- s = INTERNAL_DISASSEMBLER_ERROR;
- break;
- }
- oappend (s);
-}
-
-static void
-OP_IMREG (int code, int sizeflag)
-{
- const char *s;
-
- switch (code)
- {
- case indir_dx_reg:
- if (intel_syntax)
- s = "dx";
- else
- s = "(%dx)";
- break;
- case ax_reg: case cx_reg: case dx_reg: case bx_reg:
- case sp_reg: case bp_reg: case si_reg: case di_reg:
- s = names16[code - ax_reg];
- break;
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- s = names_seg[code - es_reg];
- break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
- USED_REX (0);
- if (rex)
- s = names8rex[code - al_reg];
- else
- s = names8[code - al_reg];
- break;
- case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
- case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
- USED_REX (REX_W);
- if (rex & REX_W)
- s = names64[code - eAX_reg];
- else if (sizeflag & DFLAG)
- s = names32[code - eAX_reg];
- else
- s = names16[code - eAX_reg];
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case z_mode_ax_reg:
- if ((rex & REX_W) || (sizeflag & DFLAG))
- s = *names32;
- else
- s = *names16;
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- default:
- s = INTERNAL_DISASSEMBLER_ERROR;
- break;
- }
- oappend (s);
-}
-
-static void
-OP_I (int bytemode, int sizeflag)
-{
- bfd_signed_vma op;
- bfd_signed_vma mask = -1;
-
- switch (bytemode)
- {
- case b_mode:
- fetch_data(the_info, codep + 1);
- op = *codep++;
- mask = 0xff;
- break;
- case q_mode:
- if (address_mode == mode_64bit)
- {
- op = get32s ();
- break;
- }
- /* Fall through. */
- case v_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- op = get32s ();
- else if (sizeflag & DFLAG)
- {
- op = get32 ();
- mask = 0xffffffff;
- }
- else
- {
- op = get16 ();
- mask = 0xfffff;
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case w_mode:
- mask = 0xfffff;
- op = get16 ();
- break;
- case const_1_mode:
- if (intel_syntax)
- oappend ("1");
- return;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
-
- op &= mask;
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, sizeof(scratchbuf) - 1, 1, op);
- oappend (scratchbuf + intel_syntax);
- scratchbuf[0] = '\0';
-}
-
-static void
-OP_I64 (int bytemode, int sizeflag)
-{
- bfd_signed_vma op;
- bfd_signed_vma mask = -1;
-
- if (address_mode != mode_64bit)
- {
- OP_I (bytemode, sizeflag);
- return;
- }
-
- switch (bytemode)
- {
- case b_mode:
- fetch_data(the_info, codep + 1);
- op = *codep++;
- mask = 0xff;
- break;
- case v_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- op = get64 ();
- else if (sizeflag & DFLAG)
- {
- op = get32 ();
- mask = 0xffffffff;
- }
- else
- {
- op = get16 ();
- mask = 0xfffff;
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case w_mode:
- mask = 0xfffff;
- op = get16 ();
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
-
- op &= mask;
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, sizeof(scratchbuf) - 1, 1, op);
- oappend (scratchbuf + intel_syntax);
- scratchbuf[0] = '\0';
-}
-
-static void
-OP_sI (int bytemode, int sizeflag)
-{
- bfd_signed_vma op;
-
- switch (bytemode)
- {
- case b_mode:
- fetch_data(the_info, codep + 1);
- op = *codep++;
- if ((op & 0x80) != 0)
- op -= 0x100;
- break;
- case v_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- op = get32s ();
- else if (sizeflag & DFLAG)
- {
- op = get32s ();
- }
- else
- {
- op = get16 ();
- if ((op & 0x8000) != 0)
- op -= 0x10000;
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- case w_mode:
- op = get16 ();
- if ((op & 0x8000) != 0)
- op -= 0x10000;
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
-
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, sizeof(scratchbuf) - 1, 1, op);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_J (int bytemode, int sizeflag)
-{
- bfd_vma disp;
- bfd_vma mask = -1;
- bfd_vma segment = 0;
-
- switch (bytemode)
- {
- case b_mode:
- fetch_data(the_info, codep + 1);
- disp = *codep++;
- if ((disp & 0x80) != 0)
- disp -= 0x100;
- break;
- case v_mode:
- if ((sizeflag & DFLAG) || (rex & REX_W))
- disp = get32s ();
- else
- {
- disp = get16 ();
- if ((disp & 0x8000) != 0)
- disp -= 0x10000;
- /* In 16bit mode, address is wrapped around at 64k within
- the same segment. Otherwise, a data16 prefix on a jump
- instruction means that the pc is masked to 16 bits after
- the displacement is added! */
- mask = 0xffff;
- if ((prefixes & PREFIX_DATA) == 0)
- segment = ((start_pc + codep - start_codep)
- & ~((bfd_vma) 0xffff));
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
- disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
- set_op (disp, 0);
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1, disp);
- oappend (scratchbuf);
-}
-
-static void
-OP_SEG (int bytemode, int sizeflag)
-{
- if (bytemode == w_mode)
- oappend (names_seg[modrm.reg]);
- else
- OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
-}
-
-static void
-OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
-{
- int seg, offset;
-
- if (sizeflag & DFLAG)
- {
- offset = get32 ();
- seg = get16 ();
- }
- else
- {
- offset = get16 ();
- seg = get16 ();
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (intel_syntax)
- snprintf (scratchbuf, sizeof(scratchbuf), "0x%x:0x%x", seg, offset);
- else
- snprintf (scratchbuf, sizeof(scratchbuf), "$0x%x,$0x%x", seg, offset);
- oappend (scratchbuf);
-}
-
-static void
-OP_OFF (int bytemode, int sizeflag)
-{
- bfd_vma off;
-
- if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
-
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- off = get32 ();
- else
- off = get16 ();
-
- if (intel_syntax)
- {
- if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- }
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1, off);
- oappend (scratchbuf);
-}
-
-static void
-OP_OFF64 (int bytemode, int sizeflag)
-{
- bfd_vma off;
-
- if (address_mode != mode_64bit
- || (prefixes & PREFIX_ADDR))
- {
- OP_OFF (bytemode, sizeflag);
- return;
- }
-
- if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
- intel_operand_size (bytemode, sizeflag);
- append_seg ();
-
- off = get64 ();
-
- if (intel_syntax)
- {
- if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
- {
- oappend (names_seg[ds_reg - es_reg]);
- oappend (":");
- }
- }
- print_operand_value (scratchbuf, sizeof(scratchbuf), 1, off);
- oappend (scratchbuf);
-}
-
-static void
-ptr_reg (int code, int sizeflag)
-{
- const char *s;
-
- *obufp++ = open_char;
- used_prefixes |= (prefixes & PREFIX_ADDR);
- if (address_mode == mode_64bit)
- {
- if (!(sizeflag & AFLAG))
- s = names32[code - eAX_reg];
- else
- s = names64[code - eAX_reg];
- }
- else if (sizeflag & AFLAG)
- s = names32[code - eAX_reg];
- else
- s = names16[code - eAX_reg];
- oappend (s);
- *obufp++ = close_char;
- *obufp = 0;
-}
-
-static void
-OP_ESreg (int code, int sizeflag)
-{
- if (intel_syntax)
- {
- switch (codep[-1])
- {
- case 0x6d: /* insw/insl */
- intel_operand_size (z_mode, sizeflag);
- break;
- case 0xa5: /* movsw/movsl/movsq */
- case 0xa7: /* cmpsw/cmpsl/cmpsq */
- case 0xab: /* stosw/stosl */
- case 0xaf: /* scasw/scasl */
- intel_operand_size (v_mode, sizeflag);
- break;
- default:
- intel_operand_size (b_mode, sizeflag);
- }
- }
- oappend ("%es:" + intel_syntax);
- ptr_reg (code, sizeflag);
-}
-
-static void
-OP_DSreg (int code, int sizeflag)
-{
- if (intel_syntax)
- {
- switch (codep[-1])
- {
- case 0x6f: /* outsw/outsl */
- intel_operand_size (z_mode, sizeflag);
- break;
- case 0xa5: /* movsw/movsl/movsq */
- case 0xa7: /* cmpsw/cmpsl/cmpsq */
- case 0xad: /* lodsw/lodsl/lodsq */
- intel_operand_size (v_mode, sizeflag);
- break;
- default:
- intel_operand_size (b_mode, sizeflag);
- }
- }
- if ((prefixes
- & (PREFIX_CS
- | PREFIX_DS
- | PREFIX_SS
- | PREFIX_ES
- | PREFIX_FS
- | PREFIX_GS)) == 0)
- prefixes |= PREFIX_DS;
- append_seg ();
- ptr_reg (code, sizeflag);
-}
-
-static void
-OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int add = 0;
- if (rex & REX_R)
- {
- USED_REX (REX_R);
- add = 8;
- }
- else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
- {
- used_prefixes |= PREFIX_LOCK;
- add = 8;
- }
- snprintf (scratchbuf, sizeof(scratchbuf), "%%cr%d", modrm.reg + add);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int add = 0;
- USED_REX (REX_R);
- if (rex & REX_R)
- add = 8;
- if (intel_syntax)
- snprintf (scratchbuf, sizeof(scratchbuf), "db%d", modrm.reg + add);
- else
- snprintf (scratchbuf, sizeof(scratchbuf), "%%db%d", modrm.reg + add);
- oappend (scratchbuf);
-}
-
-static void
-OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- snprintf (scratchbuf, sizeof(scratchbuf), "%%tr%d", modrm.reg);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_R (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- OP_E (bytemode, sizeflag);
- else
- BadOp ();
-}
-
-static void
-OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- {
- int add = 0;
- USED_REX (REX_R);
- if (rex & REX_R)
- add = 8;
- snprintf (scratchbuf, sizeof(scratchbuf), "%%xmm%d", modrm.reg + add);
- }
- else
- snprintf (scratchbuf, sizeof(scratchbuf), "%%mm%d", modrm.reg);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int add = 0;
- USED_REX (REX_R);
- if (rex & REX_R)
- add = 8;
- snprintf (scratchbuf, sizeof(scratchbuf), "%%xmm%d", modrm.reg + add);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_EM (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3)
- {
- if (intel_syntax && bytemode == v_mode)
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
- return;
- }
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- {
- int add = 0;
-
- USED_REX (REX_B);
- if (rex & REX_B)
- add = 8;
- snprintf (scratchbuf, sizeof(scratchbuf), "%%xmm%d", modrm.rm + add);
- }
- else
- snprintf (scratchbuf, sizeof(scratchbuf), "%%mm%d", modrm.rm);
- oappend (scratchbuf + intel_syntax);
-}
-
-/* cvt* are the only instructions in sse2 which have
- both SSE and MMX operands and also have 0x66 prefix
- in their opcode. 0x66 was originally used to differentiate
- between SSE and MMX instruction(operands). So we have to handle the
- cvt* separately using OP_EMC and OP_MXC */
-static void
-OP_EMC (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3)
- {
- if (intel_syntax && bytemode == v_mode)
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
- return;
- }
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- used_prefixes |= (prefixes & PREFIX_DATA);
- snprintf (scratchbuf, sizeof(scratchbuf), "%%mm%d", modrm.rm);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- used_prefixes |= (prefixes & PREFIX_DATA);
- snprintf (scratchbuf, sizeof(scratchbuf), "%%mm%d", modrm.reg);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_EX (int bytemode, int sizeflag)
-{
- int add = 0;
- if (modrm.mod != 3)
- {
- OP_E (bytemode, sizeflag);
- return;
- }
- USED_REX (REX_B);
- if (rex & REX_B)
- add = 8;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- snprintf (scratchbuf, sizeof(scratchbuf), "%%xmm%d", modrm.rm + add);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-OP_MS (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- OP_EM (bytemode, sizeflag);
- else
- BadOp ();
-}
-
-static void
-OP_XS (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- OP_EX (bytemode, sizeflag);
- else
- BadOp ();
-}
-
-static void
-OP_M (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
- BadOp ();
- else
- OP_E (bytemode, sizeflag);
-}
-
-static void
-OP_0f07 (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3 || modrm.rm != 0)
- BadOp ();
- else
- OP_E (bytemode, sizeflag);
-}
-
-static void
-OP_0fae (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- {
- if (modrm.reg == 7)
- strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
-
- if (modrm.reg < 5 || modrm.rm != 0)
- {
- BadOp (); /* bad sfence, mfence, or lfence */
- return;
- }
- }
- else if (modrm.reg != 7)
- {
- BadOp (); /* bad clflush */
- return;
- }
-
- OP_E (bytemode, sizeflag);
-}
-
-/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
- 32bit mode and "xchg %rax,%rax" in 64bit mode. */
-
-static void
-NOP_Fixup1 (int bytemode, int sizeflag)
-{
- if ((prefixes & PREFIX_DATA) != 0
- || (rex != 0
- && rex != 0x48
- && address_mode == mode_64bit))
- OP_REG (bytemode, sizeflag);
- else
- strcpy (obuf, "nop");
-}
-
-static void
-NOP_Fixup2 (int bytemode, int sizeflag)
-{
- if ((prefixes & PREFIX_DATA) != 0
- || (rex != 0
- && rex != 0x48
- && address_mode == mode_64bit))
- OP_IMREG (bytemode, sizeflag);
-}
-
-static const char *Suffix3DNow[] = {
-/* 00 */ NULL, NULL, NULL, NULL,
-/* 04 */ NULL, NULL, NULL, NULL,
-/* 08 */ NULL, NULL, NULL, NULL,
-/* 0C */ "pi2fw", "pi2fd", NULL, NULL,
-/* 10 */ NULL, NULL, NULL, NULL,
-/* 14 */ NULL, NULL, NULL, NULL,
-/* 18 */ NULL, NULL, NULL, NULL,
-/* 1C */ "pf2iw", "pf2id", NULL, NULL,
-/* 20 */ NULL, NULL, NULL, NULL,
-/* 24 */ NULL, NULL, NULL, NULL,
-/* 28 */ NULL, NULL, NULL, NULL,
-/* 2C */ NULL, NULL, NULL, NULL,
-/* 30 */ NULL, NULL, NULL, NULL,
-/* 34 */ NULL, NULL, NULL, NULL,
-/* 38 */ NULL, NULL, NULL, NULL,
-/* 3C */ NULL, NULL, NULL, NULL,
-/* 40 */ NULL, NULL, NULL, NULL,
-/* 44 */ NULL, NULL, NULL, NULL,
-/* 48 */ NULL, NULL, NULL, NULL,
-/* 4C */ NULL, NULL, NULL, NULL,
-/* 50 */ NULL, NULL, NULL, NULL,
-/* 54 */ NULL, NULL, NULL, NULL,
-/* 58 */ NULL, NULL, NULL, NULL,
-/* 5C */ NULL, NULL, NULL, NULL,
-/* 60 */ NULL, NULL, NULL, NULL,
-/* 64 */ NULL, NULL, NULL, NULL,
-/* 68 */ NULL, NULL, NULL, NULL,
-/* 6C */ NULL, NULL, NULL, NULL,
-/* 70 */ NULL, NULL, NULL, NULL,
-/* 74 */ NULL, NULL, NULL, NULL,
-/* 78 */ NULL, NULL, NULL, NULL,
-/* 7C */ NULL, NULL, NULL, NULL,
-/* 80 */ NULL, NULL, NULL, NULL,
-/* 84 */ NULL, NULL, NULL, NULL,
-/* 88 */ NULL, NULL, "pfnacc", NULL,
-/* 8C */ NULL, NULL, "pfpnacc", NULL,
-/* 90 */ "pfcmpge", NULL, NULL, NULL,
-/* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
-/* 98 */ NULL, NULL, "pfsub", NULL,
-/* 9C */ NULL, NULL, "pfadd", NULL,
-/* A0 */ "pfcmpgt", NULL, NULL, NULL,
-/* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
-/* A8 */ NULL, NULL, "pfsubr", NULL,
-/* AC */ NULL, NULL, "pfacc", NULL,
-/* B0 */ "pfcmpeq", NULL, NULL, NULL,
-/* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
-/* B8 */ NULL, NULL, NULL, "pswapd",
-/* BC */ NULL, NULL, NULL, "pavgusb",
-/* C0 */ NULL, NULL, NULL, NULL,
-/* C4 */ NULL, NULL, NULL, NULL,
-/* C8 */ NULL, NULL, NULL, NULL,
-/* CC */ NULL, NULL, NULL, NULL,
-/* D0 */ NULL, NULL, NULL, NULL,
-/* D4 */ NULL, NULL, NULL, NULL,
-/* D8 */ NULL, NULL, NULL, NULL,
-/* DC */ NULL, NULL, NULL, NULL,
-/* E0 */ NULL, NULL, NULL, NULL,
-/* E4 */ NULL, NULL, NULL, NULL,
-/* E8 */ NULL, NULL, NULL, NULL,
-/* EC */ NULL, NULL, NULL, NULL,
-/* F0 */ NULL, NULL, NULL, NULL,
-/* F4 */ NULL, NULL, NULL, NULL,
-/* F8 */ NULL, NULL, NULL, NULL,
-/* FC */ NULL, NULL, NULL, NULL,
-};
-
-static void
-OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- const char *mnemonic;
-
- fetch_data(the_info, codep + 1);
- /* AMD 3DNow! instructions are specified by an opcode suffix in the
- place where an 8-bit immediate would normally go. ie. the last
- byte of the instruction. */
- obufp = obuf + strlen (obuf);
- mnemonic = Suffix3DNow[*codep++ & 0xff];
- if (mnemonic)
- oappend (mnemonic);
- else
- {
- /* Since a variable sized modrm/sib chunk is between the start
- of the opcode (0x0f0f) and the opcode suffix, we need to do
- all the modrm processing first, and don't know until now that
- we have a bad opcode. This necessitates some cleaning up. */
- op_out[0][0] = '\0';
- op_out[1][0] = '\0';
- BadOp ();
- }
-}
-
-static const char *simd_cmp_op[] = {
- "eq",
- "lt",
- "le",
- "unord",
- "neq",
- "nlt",
- "nle",
- "ord"
-};
-
-static void
-OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- unsigned int cmp_type;
-
- fetch_data(the_info, codep + 1);
- obufp = obuf + strlen (obuf);
- cmp_type = *codep++ & 0xff;
- if (cmp_type < 8)
- {
- char suffix1 = 'p', suffix2 = 's';
- used_prefixes |= (prefixes & PREFIX_REPZ);
- if (prefixes & PREFIX_REPZ)
- suffix1 = 's';
- else
- {
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- suffix2 = 'd';
- else
- {
- used_prefixes |= (prefixes & PREFIX_REPNZ);
- if (prefixes & PREFIX_REPNZ)
- suffix1 = 's', suffix2 = 'd';
- }
- }
- snprintf (scratchbuf, sizeof(scratchbuf), "cmp%s%c%c",
- simd_cmp_op[cmp_type], suffix1, suffix2);
- used_prefixes |= (prefixes & PREFIX_REPZ);
- oappend (scratchbuf);
- }
- else
- {
- /* We have a bad extension byte. Clean up. */
- op_out[0][0] = '\0';
- op_out[1][0] = '\0';
- BadOp ();
- }
-}
-
-static void
-SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED)
-{
- /* Change movlps/movhps to movhlps/movlhps for 2 register operand
- forms of these instructions. */
- if (modrm.mod == 3)
- {
- char *p = obuf + strlen (obuf);
- *(p + 1) = '\0';
- *p = *(p - 1);
- *(p - 1) = *(p - 2);
- *(p - 2) = *(p - 3);
- *(p - 3) = extrachar;
- }
-}
-
-static void
-PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
-{
- if (modrm.mod == 3 && modrm.reg == 1 && modrm.rm <= 1)
- {
- /* Override "sidt". */
- size_t olen = strlen (obuf);
- char *p = obuf + olen - 4;
- const char * const *names = (address_mode == mode_64bit
- ? names64 : names32);
-
- /* We might have a suffix when disassembling with -Msuffix. */
- if (*p == 'i')
- --p;
-
- /* Remove "addr16/addr32" if we aren't in Intel mode. */
- if (!intel_syntax
- && (prefixes & PREFIX_ADDR)
- && olen >= (4 + 7)
- && *(p - 1) == ' '
- && strncmp (p - 7, "addr", 4) == 0
- && (strncmp (p - 3, "16", 2) == 0
- || strncmp (p - 3, "32", 2) == 0))
- p -= 7;
-
- if (modrm.rm)
- {
- /* mwait %eax,%ecx */
- strcpy (p, "mwait");
- if (!intel_syntax)
- strcpy (op_out[0], names[0]);
- }
- else
- {
- /* monitor %eax,%ecx,%edx" */
- strcpy (p, "monitor");
- if (!intel_syntax)
- {
- const char * const *op1_names;
- if (!(prefixes & PREFIX_ADDR))
- op1_names = (address_mode == mode_16bit
- ? names16 : names);
- else
- {
- op1_names = (address_mode != mode_32bit
- ? names32 : names16);
- used_prefixes |= PREFIX_ADDR;
- }
- strcpy (op_out[0], op1_names[0]);
- strcpy (op_out[2], names[2]);
- }
- }
- if (!intel_syntax)
- {
- strcpy (op_out[1], names[1]);
- two_source_ops = 1;
- }
-
- codep++;
- }
- else
- OP_M (0, sizeflag);
-}
-
-static void
-SVME_Fixup (int bytemode, int sizeflag)
-{
- const char *alt;
- char *p;
-
- switch (*codep)
- {
- case 0xd8:
- alt = "vmrun";
- break;
- case 0xd9:
- alt = "vmmcall";
- break;
- case 0xda:
- alt = "vmload";
- break;
- case 0xdb:
- alt = "vmsave";
- break;
- case 0xdc:
- alt = "stgi";
- break;
- case 0xdd:
- alt = "clgi";
- break;
- case 0xde:
- alt = "skinit";
- break;
- case 0xdf:
- alt = "invlpga";
- break;
- default:
- OP_M (bytemode, sizeflag);
- return;
- }
- /* Override "lidt". */
- p = obuf + strlen (obuf) - 4;
- /* We might have a suffix. */
- if (*p == 'i')
- --p;
- strcpy (p, alt);
- if (!(prefixes & PREFIX_ADDR))
- {
- ++codep;
- return;
- }
- used_prefixes |= PREFIX_ADDR;
- switch (*codep++)
- {
- case 0xdf:
- strcpy (op_out[1], names32[1]);
- two_source_ops = 1;
- /* Fall through. */
- case 0xd8:
- case 0xda:
- case 0xdb:
- *obufp++ = open_char;
- if (address_mode == mode_64bit || (sizeflag & AFLAG))
- alt = names32[0];
- else
- alt = names16[0];
- strcpy (obufp, alt);
- obufp += strlen (alt);
- *obufp++ = close_char;
- *obufp = '\0';
- break;
- }
-}
-
-static void
-INVLPG_Fixup (int bytemode, int sizeflag)
-{
- const char *alt;
-
- switch (*codep)
- {
- case 0xf8:
- alt = "swapgs";
- break;
- case 0xf9:
- alt = "rdtscp";
- break;
- default:
- OP_M (bytemode, sizeflag);
- return;
- }
- /* Override "invlpg". */
- strcpy (obuf + strlen (obuf) - 6, alt);
- codep++;
-}
-
-static void
-BadOp (void)
-{
- /* Throw away prefixes and 1st. opcode byte. */
- codep = insn_codep + 1;
- oappend ("(bad)");
-}
-
-static void
-VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
-{
- if (modrm.mod == 3
- && modrm.reg == 0
- && modrm.rm >=1
- && modrm.rm <= 4)
- {
- /* Override "sgdt". */
- char *p = obuf + strlen (obuf) - 4;
-
- /* We might have a suffix when disassembling with -Msuffix. */
- if (*p == 'g')
- --p;
-
- switch (modrm.rm)
- {
- case 1:
- strcpy (p, "vmcall");
- break;
- case 2:
- strcpy (p, "vmlaunch");
- break;
- case 3:
- strcpy (p, "vmresume");
- break;
- case 4:
- strcpy (p, "vmxoff");
- break;
- }
-
- codep++;
- }
- else
- OP_E (0, sizeflag);
-}
-
-static void
-OP_VMX (int bytemode, int sizeflag)
-{
- used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
- if (prefixes & PREFIX_DATA)
- strcpy (obuf, "vmclear");
- else if (prefixes & PREFIX_REPZ)
- strcpy (obuf, "vmxon");
- else
- strcpy (obuf, "vmptrld");
- OP_E (bytemode, sizeflag);
-}
-
-static void
-REP_Fixup (int bytemode, int sizeflag)
-{
- /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
- lods and stos. */
- size_t ilen = 0;
-
- if (prefixes & PREFIX_REPZ)
- switch (*insn_codep)
- {
- case 0x6e: /* outsb */
- case 0x6f: /* outsw/outsl */
- case 0xa4: /* movsb */
- case 0xa5: /* movsw/movsl/movsq */
- if (!intel_syntax)
- ilen = 5;
- else
- ilen = 4;
- break;
- case 0xaa: /* stosb */
- case 0xab: /* stosw/stosl/stosq */
- case 0xac: /* lodsb */
- case 0xad: /* lodsw/lodsl/lodsq */
- if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
- ilen = 5;
- else
- ilen = 4;
- break;
- case 0x6c: /* insb */
- case 0x6d: /* insl/insw */
- if (!intel_syntax)
- ilen = 4;
- else
- ilen = 3;
- break;
- default:
- abort ();
- break;
- }
-
- if (ilen != 0)
- {
- size_t olen;
- char *p;
-
- olen = strlen (obuf);
- p = obuf + olen - ilen - 1 - 4;
- /* Handle "repz [addr16|addr32]". */
- if ((prefixes & PREFIX_ADDR))
- p -= 1 + 6;
-
- memmove (p + 3, p + 4, olen - (p + 3 - obuf));
- }
-
- switch (bytemode)
- {
- case al_reg:
- case eAX_reg:
- case indir_dx_reg:
- OP_IMREG (bytemode, sizeflag);
- break;
- case eDI_reg:
- OP_ESreg (bytemode, sizeflag);
- break;
- case eSI_reg:
- OP_DSreg (bytemode, sizeflag);
- break;
- default:
- abort ();
- break;
- }
-}
-
-static void
-CMPXCHG8B_Fixup (int bytemode, int sizeflag)
-{
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- /* Change cmpxchg8b to cmpxchg16b. */
- char *p = obuf + strlen (obuf) - 2;
- strcpy (p, "16b");
- bytemode = o_mode;
- }
- OP_M (bytemode, sizeflag);
-}
-
-static void
-XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
-{
- snprintf (scratchbuf, sizeof(scratchbuf), "%%xmm%d", reg);
- oappend (scratchbuf + intel_syntax);
-}
-
-static void
-CRC32_Fixup (int bytemode, int sizeflag)
-{
- /* Add proper suffix to "crc32". */
- char *p = obuf + strlen (obuf);
-
- switch (bytemode)
- {
- case b_mode:
- if (intel_syntax)
- break;
-
- *p++ = 'b';
- break;
- case v_mode:
- if (intel_syntax)
- break;
-
- USED_REX (REX_W);
- if (rex & REX_W)
- *p++ = 'q';
- else if (sizeflag & DFLAG)
- *p++ = 'l';
- else
- *p++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
- *p = '\0';
-
- if (modrm.mod == 3)
- {
- int add;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- USED_REX (REX_B);
- add = (rex & REX_B) ? 8 : 0;
- if (bytemode == b_mode)
- {
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.rm + add]);
- else
- oappend (names8[modrm.rm + add]);
- }
- else
- {
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.rm + add]);
- else if ((prefixes & PREFIX_DATA))
- oappend (names16[modrm.rm + add]);
- else
- oappend (names32[modrm.rm + add]);
- }
- }
- else
- OP_E (bytemode, sizeflag);
-}
diff --git a/disas/meson.build b/disas/meson.build
index e3e1b67923..7da48ea74a 100644
--- a/disas/meson.build
+++ b/disas/meson.build
@@ -4,17 +4,14 @@ subdir('libvixl')
common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c'))
common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc'))
common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss)
-common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c'))
common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
common_ss.add(when: 'CONFIG_HEXAGON_DIS', if_true: files('hexagon.c'))
common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
-common_ss.add(when: 'CONFIG_I386_DIS', if_true: files('i386.c'))
common_ss.add(when: 'CONFIG_M68K_DIS', if_true: files('m68k.c'))
common_ss.add(when: 'CONFIG_MICROBLAZE_DIS', if_true: files('microblaze.c'))
common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c'))
common_ss.add(when: 'CONFIG_NANOMIPS_DIS', if_true: files('nanomips.cpp'))
common_ss.add(when: 'CONFIG_NIOS2_DIS', if_true: files('nios2.c'))
-common_ss.add(when: 'CONFIG_PPC_DIS', if_true: files('ppc.c'))
common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('riscv.c'))
common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
diff --git a/disas/ppc.c b/disas/ppc.c
deleted file mode 100644
index 02be878198..0000000000
--- a/disas/ppc.c
+++ /dev/null
@@ -1,5435 +0,0 @@
-/* ppc-dis.c -- Disassemble PowerPC instructions
- Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
- Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not,
-see <http://www.gnu.org/licenses/>. */
-#include "qemu/osdep.h"
-#include "disas/dis-asm.h"
-#define BFD_DEFAULT_TARGET_SIZE 64
-
-/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support
-
-This file is part of GDB, GAS, and the GNU binutils.
-
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
-
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not,
-see <http://www.gnu.org/licenses/>. */
-
-/* The opcode table is an array of struct powerpc_opcode. */
-
-struct powerpc_opcode
-{
- /* The opcode name. */
- const char *name;
-
- /* The opcode itself. Those bits which will be filled in with
- operands are zeroes. */
- unsigned long opcode;
-
- /* The opcode mask. This is used by the disassembler. This is a
- mask containing ones indicating those bits which must match the
- opcode field, and zeroes indicating those bits which need not
- match (and are presumably filled in by operands). */
- unsigned long mask;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors support the instructions. The defined values
- are listed below. */
- unsigned long flags;
-
- /* An array of operand codes. Each code is an index into the
- operand table. They appear in the order which the operands must
- appear in assembly code, and are terminated by a zero. */
- unsigned char operands[8];
-};
-
-/* The table itself is sorted by major opcode number, and is otherwise
- in the order in which the disassembler should consider
- instructions. */
-extern const struct powerpc_opcode powerpc_opcodes[];
-extern const int powerpc_num_opcodes;
-
-/* Values defined for the flags field of a struct powerpc_opcode. */
-
-/* Opcode is defined for the PowerPC architecture. */
-#define PPC_OPCODE_PPC 1
-
-/* Opcode is defined for the POWER (RS/6000) architecture. */
-#define PPC_OPCODE_POWER 2
-
-/* Opcode is defined for the POWER2 (Rios 2) architecture. */
-#define PPC_OPCODE_POWER2 4
-
-/* Opcode is only defined on 32 bit architectures. */
-#define PPC_OPCODE_32 8
-
-/* Opcode is only defined on 64 bit architectures. */
-#define PPC_OPCODE_64 0x10
-
-/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
- is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
- but it also supports many additional POWER instructions. */
-#define PPC_OPCODE_601 0x20
-
-/* Opcode is supported in both the Power and PowerPC architectures
- (ie, compiler's -mcpu=common or assembler's -mcom). */
-#define PPC_OPCODE_COMMON 0x40
-
-/* Opcode is supported for any Power or PowerPC platform (this is
- for the assembler's -many option, and it eliminates duplicates). */
-#define PPC_OPCODE_ANY 0x80
-
-/* Opcode is supported as part of the 64-bit bridge. */
-#define PPC_OPCODE_64_BRIDGE 0x100
-
-/* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC 0x200
-
-/* Opcode is supported by PowerPC 403 processor. */
-#define PPC_OPCODE_403 0x400
-
-/* Opcode is supported by PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE 0x800
-
-/* Opcode is only supported by 64-bit PowerPC BookE processor. */
-#define PPC_OPCODE_BOOKE64 0x1000
-
-/* Opcode is supported by PowerPC 440 processor. */
-#define PPC_OPCODE_440 0x2000
-
-/* Opcode is only supported by Power4 architecture. */
-#define PPC_OPCODE_POWER4 0x4000
-
-/* Opcode isn't supported by Power4 architecture. */
-#define PPC_OPCODE_NOPOWER4 0x8000
-
-/* Opcode is only supported by POWERPC Classic architecture. */
-#define PPC_OPCODE_CLASSIC 0x10000
-
-/* Opcode is only supported by e500x2 Core. */
-#define PPC_OPCODE_SPE 0x20000
-
-/* Opcode is supported by e500x2 Integer select APU. */
-#define PPC_OPCODE_ISEL 0x40000
-
-/* Opcode is an e500 SPE floating point instruction. */
-#define PPC_OPCODE_EFS 0x80000
-
-/* Opcode is supported by branch locking APU. */
-#define PPC_OPCODE_BRLOCK 0x100000
-
-/* Opcode is supported by performance monitor APU. */
-#define PPC_OPCODE_PMR 0x200000
-
-/* Opcode is supported by cache locking APU. */
-#define PPC_OPCODE_CACHELCK 0x400000
-
-/* Opcode is supported by machine check APU. */
-#define PPC_OPCODE_RFMCI 0x800000
-
-/* Opcode is only supported by Power5 architecture. */
-#define PPC_OPCODE_POWER5 0x1000000
-
-/* Opcode is supported by PowerPC e300 family. */
-#define PPC_OPCODE_E300 0x2000000
-
-/* Opcode is only supported by Power6 architecture. */
-#define PPC_OPCODE_POWER6 0x4000000
-
-/* Opcode is only supported by PowerPC Cell family. */
-#define PPC_OPCODE_CELL 0x8000000
-
-/* A macro to extract the major opcode from an instruction. */
-#define PPC_OP(i) (((i) >> 26) & 0x3f)
-
-/* The operands table is an array of struct powerpc_operand. */
-
-struct powerpc_operand
-{
- /* A bitmask of bits in the operand. */
- unsigned int bitm;
-
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
- int shift;
-
- /* Insertion function. This is used by the assembler. To insert an
- operand value into an instruction, check this field.
-
- If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
- (i is the instruction which we are filling in, o is a pointer to
- this structure, and op is the operand value).
-
- If this field is not NULL, then simply call it with the
- instruction and the operand value. It will return the new value
- of the instruction. If the ERRMSG argument is not NULL, then if
- the operand value is illegal, *ERRMSG will be set to a warning
- string (the operand will be inserted in any case). If the
- operand value is legal, *ERRMSG will be unchanged (most operands
- can accept any value). */
- unsigned long (*insert)
- (unsigned long instruction, long op, int dialect, const char **errmsg);
-
- /* Extraction function. This is used by the disassembler. To
- extract this operand type from an instruction, check this field.
-
- If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
- if ((o->flags & PPC_OPERAND_SIGNED) != 0)
- sign_extend (op);
- (i is the instruction, o is a pointer to this structure, and op
- is the result).
-
- If this field is not NULL, then simply call it with the
- instruction value. It will return the value of the operand. If
- the INVALID argument is not NULL, *INVALID will be set to
- non-zero if this operand type can not actually be extracted from
- this operand (i.e., the instruction does not match). If the
- operand is valid, *INVALID will not be changed. */
- long (*extract) (unsigned long instruction, int dialect, int *invalid);
-
- /* One bit syntax flags. */
- unsigned long flags;
-};
-
-/* Elements in the table are retrieved by indexing with values from
- the operands field of the powerpc_opcodes table. */
-
-extern const struct powerpc_operand powerpc_operands[];
-extern const unsigned int num_powerpc_operands;
-
-/* Values defined for the flags field of a struct powerpc_operand. */
-
-/* This operand takes signed values. */
-#define PPC_OPERAND_SIGNED (0x1)
-
-/* This operand takes signed values, but also accepts a full positive
- range of values when running in 32 bit mode. That is, if bits is
- 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
- this flag is ignored. */
-#define PPC_OPERAND_SIGNOPT (0x2)
-
-/* This operand does not actually exist in the assembler input. This
- is used to support extended mnemonics such as mr, for which two
- operands fields are identical. The assembler should call the
- insert function with any op value. The disassembler should call
- the extract function, ignore the return value, and check the value
- placed in the valid argument. */
-#define PPC_OPERAND_FAKE (0x4)
-
-/* The next operand should be wrapped in parentheses rather than
- separated from this one by a comma. This is used for the load and
- store instructions which want their operands to look like
- reg,displacement(reg)
- */
-#define PPC_OPERAND_PARENS (0x8)
-
-/* This operand may use the symbolic names for the CR fields, which
- are
- lt 0 gt 1 eq 2 so 3 un 3
- cr0 0 cr1 1 cr2 2 cr3 3
- cr4 4 cr5 5 cr6 6 cr7 7
- These may be combined arithmetically, as in cr2*4+gt. These are
- only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
-
-/* This operand names a register. The disassembler uses this to print
- register names with a leading 'r'. */
-#define PPC_OPERAND_GPR (0x20)
-
-/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
-#define PPC_OPERAND_GPR_0 (0x40)
-
-/* This operand names a floating point register. The disassembler
- prints these with a leading 'f'. */
-#define PPC_OPERAND_FPR (0x80)
-
-/* This operand is a relative branch displacement. The disassembler
- prints these symbolically if possible. */
-#define PPC_OPERAND_RELATIVE (0x100)
-
-/* This operand is an absolute branch address. The disassembler
- prints these symbolically if possible. */
-#define PPC_OPERAND_ABSOLUTE (0x200)
-
-/* This operand is optional, and is zero if omitted. This is used for
- example, in the optional BF field in the comparison instructions. The
- assembler must count the number of operands remaining on the line,
- and the number of operands remaining for the opcode, and decide
- whether this operand is present or not. The disassembler should
- print this operand out only if it is not zero. */
-#define PPC_OPERAND_OPTIONAL (0x400)
-
-/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
- is omitted, then for the next operand use this operand value plus
- 1, ignoring the next operand field for the opcode. This wretched
- hack is needed because the Power rotate instructions can take
- either 4 or 5 operands. The disassembler should print this operand
- out regardless of the PPC_OPERAND_OPTIONAL field. */
-#define PPC_OPERAND_NEXT (0x800)
-
-/* This operand should be regarded as a negative number for the
- purposes of overflow checking (i.e., the normal most negative
- number is disallowed and one more than the normal most positive
- number is allowed). This flag will only be set for a signed
- operand. */
-#define PPC_OPERAND_NEGATIVE (0x1000)
-
-/* This operand names a vector unit register. The disassembler
- prints these with a leading 'v'. */
-#define PPC_OPERAND_VR (0x2000)
-
-/* This operand is for the DS field in a DS form instruction. */
-#define PPC_OPERAND_DS (0x4000)
-
-/* This operand is for the DQ field in a DQ form instruction. */
-#define PPC_OPERAND_DQ (0x8000)
-
-/* Valid range of operand is 0..n rather than 0..n-1. */
-#define PPC_OPERAND_PLUS1 (0x10000)
-
-/* The POWER and PowerPC assemblers use a few macros. We keep them
- with the operands table for simplicity. The macro table is an
- array of struct powerpc_macro. */
-
-struct powerpc_macro
-{
- /* The macro name. */
- const char *name;
-
- /* The number of operands the macro takes. */
- unsigned int operands;
-
- /* One bit flags for the opcode. These are used to indicate which
- specific processors support the instructions. The values are the
- same as those for the struct powerpc_opcode flags field. */
- unsigned long flags;
-
- /* A format string to turn the macro into a normal instruction.
- Each %N in the string is replaced with operand number N (zero
- based). */
- const char *format;
-};
-
-extern const struct powerpc_macro powerpc_macros[];
-extern const int powerpc_num_macros;
-
-/* ppc-opc.c -- PowerPC opcode list
- Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
- 2005, 2006, 2007 Free Software Foundation, Inc.
- Written by Ian Lance Taylor, Cygnus Support
-
- This file is part of GDB, GAS, and the GNU binutils.
-
- GDB, GAS, and the GNU binutils are free software; you can redistribute
- them and/or modify them under the terms of the GNU General Public
- License as published by the Free Software Foundation; either version
- 2, or (at your option) any later version.
-
- GDB, GAS, and the GNU binutils are distributed in the hope that they
- will be useful, but WITHOUT ANY WARRANTY; without even the implied
- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
- the GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this file; see the file COPYING.
- If not, see <http://www.gnu.org/licenses/>. */
-
-/* This file holds the PowerPC opcode table. The opcode table
- includes almost all of the extended instruction mnemonics. This
- permits the disassembler to use them, and simplifies the assembler
- logic, at the cost of increasing the table size. The table is
- strictly constant data, so the compiler should be able to put it in
- the .text section.
-
- This file also holds the operand table. All knowledge about
- inserting operands into instructions and vice-versa is kept in this
- file. */
-
-/* Local insertion and extraction functions. */
-
-static unsigned long insert_bat (unsigned long, long, int, const char **);
-static long extract_bat (unsigned long, int, int *);
-static unsigned long insert_bba (unsigned long, long, int, const char **);
-static long extract_bba (unsigned long, int, int *);
-static unsigned long insert_bdm (unsigned long, long, int, const char **);
-static long extract_bdm (unsigned long, int, int *);
-static unsigned long insert_bdp (unsigned long, long, int, const char **);
-static long extract_bdp (unsigned long, int, int *);
-static unsigned long insert_bo (unsigned long, long, int, const char **);
-static long extract_bo (unsigned long, int, int *);
-static unsigned long insert_boe (unsigned long, long, int, const char **);
-static long extract_boe (unsigned long, int, int *);
-static unsigned long insert_fxm (unsigned long, long, int, const char **);
-static long extract_fxm (unsigned long, int, int *);
-static unsigned long insert_mbe (unsigned long, long, int, const char **);
-static long extract_mbe (unsigned long, int, int *);
-static unsigned long insert_mb6 (unsigned long, long, int, const char **);
-static long extract_mb6 (unsigned long, int, int *);
-static long extract_nb (unsigned long, int, int *);
-static unsigned long insert_nsi (unsigned long, long, int, const char **);
-static long extract_nsi (unsigned long, int, int *);
-static unsigned long insert_ral (unsigned long, long, int, const char **);
-static unsigned long insert_ram (unsigned long, long, int, const char **);
-static unsigned long insert_raq (unsigned long, long, int, const char **);
-static unsigned long insert_ras (unsigned long, long, int, const char **);
-static unsigned long insert_rbs (unsigned long, long, int, const char **);
-static long extract_rbs (unsigned long, int, int *);
-static unsigned long insert_sh6 (unsigned long, long, int, const char **);
-static long extract_sh6 (unsigned long, int, int *);
-static unsigned long insert_spr (unsigned long, long, int, const char **);
-static long extract_spr (unsigned long, int, int *);
-static unsigned long insert_sprg (unsigned long, long, int, const char **);
-static long extract_sprg (unsigned long, int, int *);
-static unsigned long insert_tbr (unsigned long, long, int, const char **);
-static long extract_tbr (unsigned long, int, int *);
-
-/* The operands table.
-
- The fields are bitm, shift, insert, extract, flags.
-
- We used to put parens around the various additions, like the one
- for BA just below. However, that caused trouble with feeble
- compilers with a limit on depth of a parenthesized expression, like
- (reportedly) the compiler in Microsoft Developer Studio 5. So we
- omit the parens, since the macros are never used in a context where
- the addition will be ambiguous. */
-
-const struct powerpc_operand powerpc_operands[] =
-{
- /* The zero index is used to indicate the end of the list of
- operands. */
-#define UNUSED 0
- { 0, 0, NULL, NULL, 0 },
-
- /* The BA field in an XL form instruction. */
-#define BA UNUSED + 1
- /* The BI field in a B form or XL form instruction. */
-#define BI BA
-#define BI_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
-
- /* The BA field in an XL form instruction when it must be the same
- as the BT field in the same instruction. */
-#define BAT BA + 1
- { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
-
- /* The BB field in an XL form instruction. */
-#define BB BAT + 1
-#define BB_MASK (0x1f << 11)
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
-
- /* The BB field in an XL form instruction when it must be the same
- as the BA field in the same instruction. */
-#define BBA BB + 1
- { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
-
- /* The BD field in a B form instruction. The lower two bits are
- forced to zero. */
-#define BD BBA + 1
- { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
-
- /* The BD field in a B form instruction when absolute addressing is
- used. */
-#define BDA BD + 1
- { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
-
- /* The BD field in a B form instruction when the - modifier is used.
- This sets the y bit of the BO field appropriately. */
-#define BDM BDA + 1
- { 0xfffc, 0, insert_bdm, extract_bdm,
- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
-
- /* The BD field in a B form instruction when the - modifier is used
- and absolute address is used. */
-#define BDMA BDM + 1
- { 0xfffc, 0, insert_bdm, extract_bdm,
- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
-
- /* The BD field in a B form instruction when the + modifier is used.
- This sets the y bit of the BO field appropriately. */
-#define BDP BDMA + 1
- { 0xfffc, 0, insert_bdp, extract_bdp,
- PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
-
- /* The BD field in a B form instruction when the + modifier is used
- and absolute addressing is used. */
-#define BDPA BDP + 1
- { 0xfffc, 0, insert_bdp, extract_bdp,
- PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
-
- /* The BF field in an X or XL form instruction. */
-#define BF BDPA + 1
- /* The CRFD field in an X form instruction. */
-#define CRFD BF
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
-
- /* The BF field in an X or XL form instruction. */
-#define BFF BF + 1
- { 0x7, 23, NULL, NULL, 0 },
-
- /* An optional BF field. This is used for comparison instructions,
- in which an omitted BF field is taken as zero. */
-#define OBF BFF + 1
- { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
-
- /* The BFA field in an X or XL form instruction. */
-#define BFA OBF + 1
- { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
-
- /* The BO field in a B form instruction. Certain values are
- illegal. */
-#define BO BFA + 1
-#define BO_MASK (0x1f << 21)
- { 0x1f, 21, insert_bo, extract_bo, 0 },
-
- /* The BO field in a B form instruction when the + or - modifier is
- used. This is like the BO field, but it must be even. */
-#define BOE BO + 1
- { 0x1e, 21, insert_boe, extract_boe, 0 },
-
-#define BH BOE + 1
- { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The BT field in an X or XL form instruction. */
-#define BT BH + 1
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
-
- /* The condition register number portion of the BI field in a B form
- or XL form instruction. This is used for the extended
- conditional branch mnemonics, which set the lower two bits of the
- BI field. This field is optional. */
-#define CR BT + 1
- { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
-
- /* The CRB field in an X form instruction. */
-#define CRB CR + 1
- /* The MB field in an M form instruction. */
-#define MB CRB
-#define MB_MASK (0x1f << 6)
- { 0x1f, 6, NULL, NULL, 0 },
-
- /* The CRFS field in an X form instruction. */
-#define CRFS CRB + 1
- { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
-
- /* The CT field in an X form instruction. */
-#define CT CRFS + 1
- /* The MO field in an mbar instruction. */
-#define MO CT
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The D field in a D form instruction. This is a displacement off
- a register, and implies that the next operand is a register in
- parentheses. */
-#define D CT + 1
- { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
- /* The DE field in a DE form instruction. This is like D, but is 12
- bits only. */
-#define DE D + 1
- { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
- /* The DES field in a DES form instruction. This is like DS, but is 14
- bits only (12 stored.) */
-#define DES DE + 1
- { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
-
- /* The DQ field in a DQ form instruction. This is like D, but the
- lower four bits are forced to zero. */
-#define DQ DES + 1
- { 0xfff0, 0, NULL, NULL,
- PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
-
- /* The DS field in a DS form instruction. This is like D, but the
- lower two bits are forced to zero. */
-#undef DS
-#define DS DQ + 1
- { 0xfffc, 0, NULL, NULL,
- PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
-
- /* The E field in a wrteei instruction. */
-#define E DS + 1
- { 0x1, 15, NULL, NULL, 0 },
-
- /* The FL1 field in a POWER SC form instruction. */
-#define FL1 E + 1
- /* The U field in an X form instruction. */
-#define U FL1
- { 0xf, 12, NULL, NULL, 0 },
-
- /* The FL2 field in a POWER SC form instruction. */
-#define FL2 FL1 + 1
- { 0x7, 2, NULL, NULL, 0 },
-
- /* The FLM field in an XFL form instruction. */
-#define FLM FL2 + 1
- { 0xff, 17, NULL, NULL, 0 },
-
- /* The FRA field in an X or A form instruction. */
-#define FRA FLM + 1
-#define FRA_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
-
- /* The FRB field in an X or A form instruction. */
-#define FRB FRA + 1
-#define FRB_MASK (0x1f << 11)
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
-
- /* The FRC field in an A form instruction. */
-#define FRC FRB + 1
-#define FRC_MASK (0x1f << 6)
- { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
-
- /* The FRS field in an X form instruction or the FRT field in a D, X
- or A form instruction. */
-#define FRS FRC + 1
-#define FRT FRS
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
-
- /* The FXM field in an XFX instruction. */
-#define FXM FRS + 1
- { 0xff, 12, insert_fxm, extract_fxm, 0 },
-
- /* Power4 version for mfcr. */
-#define FXM4 FXM + 1
- { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
-
- /* The L field in a D or X form instruction. */
-#define L FXM4 + 1
- { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The LEV field in a POWER SVC form instruction. */
-#define SVC_LEV L + 1
- { 0x7f, 5, NULL, NULL, 0 },
-
- /* The LEV field in an SC form instruction. */
-#define LEV SVC_LEV + 1
- { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The LI field in an I form instruction. The lower two bits are
- forced to zero. */
-#define LI LEV + 1
- { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
-
- /* The LI field in an I form instruction when used as an absolute
- address. */
-#define LIA LI + 1
- { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
-
- /* The LS field in an X (sync) form instruction. */
-#define LS LIA + 1
- { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The ME field in an M form instruction. */
-#define ME LS + 1
-#define ME_MASK (0x1f << 1)
- { 0x1f, 1, NULL, NULL, 0 },
-
- /* The MB and ME fields in an M form instruction expressed a single
- operand which is a bitmask indicating which bits to select. This
- is a two operand form using PPC_OPERAND_NEXT. See the
- description in opcode/ppc.h for what this means. */
-#define MBE ME + 1
- { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
- { -1, 0, insert_mbe, extract_mbe, 0 },
-
- /* The MB or ME field in an MD or MDS form instruction. The high
- bit is wrapped to the low end. */
-#define MB6 MBE + 2
-#define ME6 MB6
-#define MB6_MASK (0x3f << 5)
- { 0x3f, 5, insert_mb6, extract_mb6, 0 },
-
- /* The NB field in an X form instruction. The value 32 is stored as
- 0. */
-#define NB MB6 + 1
- { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
-
- /* The NSI field in a D form instruction. This is the same as the
- SI field, only negated. */
-#define NSI NB + 1
- { 0xffff, 0, insert_nsi, extract_nsi,
- PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
-
- /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
-#define RA NSI + 1
-#define RA_MASK (0x1f << 16)
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
-
- /* As above, but 0 in the RA field means zero, not r0. */
-#define RA0 RA + 1
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RA field in the DQ form lq instruction, which has special
- value restrictions. */
-#define RAQ RA0 + 1
- { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RA field in a D or X form instruction which is an updating
- load, which means that the RA field may not be zero and may not
- equal the RT field. */
-#define RAL RAQ + 1
- { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RA field in an lmw instruction, which has special value
- restrictions. */
-#define RAM RAL + 1
- { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RA field in a D or X form instruction which is an updating
- store or an updating floating point load, which means that the RA
- field may not be zero. */
-#define RAS RAM + 1
- { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RA field of the tlbwe instruction, which is optional. */
-#define RAOPT RAS + 1
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
-
- /* The RB field in an X, XO, M, or MDS form instruction. */
-#define RB RAOPT + 1
-#define RB_MASK (0x1f << 11)
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
-
- /* The RB field in an X form instruction when it must be the same as
- the RS field in the instruction. This is used for extended
- mnemonics like mr. */
-#define RBS RB + 1
- { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
-
- /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
- instruction or the RT field in a D, DS, X, XFX or XO form
- instruction. */
-#define RS RBS + 1
-#define RT RS
-#define RT_MASK (0x1f << 21)
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
-
- /* The RS and RT fields of the DS form stq instruction, which have
- special value restrictions. */
-#define RSQ RS + 1
-#define RTQ RSQ
- { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
-
- /* The RS field of the tlbwe instruction, which is optional. */
-#define RSO RSQ + 1
-#define RTO RSO
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
-
- /* The SH field in an X or M form instruction. */
-#define SH RSO + 1
-#define SH_MASK (0x1f << 11)
- /* The other UIMM field in a EVX form instruction. */
-#define EVUIMM SH
- { 0x1f, 11, NULL, NULL, 0 },
-
- /* The SH field in an MD form instruction. This is split. */
-#define SH6 SH + 1
-#define SH6_MASK ((0x1f << 11) | (1 << 1))
- { 0x3f, -1, insert_sh6, extract_sh6, 0 },
-
- /* The SH field of the tlbwe instruction, which is optional. */
-#define SHO SH6 + 1
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The SI field in a D form instruction. */
-#define SI SHO + 1
- { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
-
- /* The SI field in a D form instruction when we accept a wide range
- of positive values. */
-#define SISIGNOPT SI + 1
- { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
-
- /* The SPR field in an XFX form instruction. This is flipped--the
- lower 5 bits are stored in the upper 5 and vice- versa. */
-#define SPR SISIGNOPT + 1
-#define PMR SPR
-#define SPR_MASK (0x3ff << 11)
- { 0x3ff, 11, insert_spr, extract_spr, 0 },
-
- /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
-#define SPRBAT SPR + 1
-#define SPRBAT_MASK (0x3 << 17)
- { 0x3, 17, NULL, NULL, 0 },
-
- /* The SPRG register number in an XFX form m[ft]sprg instruction. */
-#define SPRG SPRBAT + 1
- { 0x1f, 16, insert_sprg, extract_sprg, 0 },
-
- /* The SR field in an X form instruction. */
-#define SR SPRG + 1
- { 0xf, 16, NULL, NULL, 0 },
-
- /* The STRM field in an X AltiVec form instruction. */
-#define STRM SR + 1
- { 0x3, 21, NULL, NULL, 0 },
-
- /* The SV field in a POWER SC form instruction. */
-#define SV STRM + 1
- { 0x3fff, 2, NULL, NULL, 0 },
-
- /* The TBR field in an XFX form instruction. This is like the SPR
- field, but it is optional. */
-#define TBR SV + 1
- { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
-
- /* The TO field in a D or X form instruction. */
-#define TO TBR + 1
-#define TO_MASK (0x1f << 21)
- { 0x1f, 21, NULL, NULL, 0 },
-
- /* The UI field in a D form instruction. */
-#define UI TO + 1
- { 0xffff, 0, NULL, NULL, 0 },
-
- /* The VA field in a VA, VX or VXR form instruction. */
-#define VA UI + 1
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
-
- /* The VB field in a VA, VX or VXR form instruction. */
-#define VB VA + 1
- { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
-
- /* The VC field in a VA form instruction. */
-#define VC VB + 1
- { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
-
- /* The VD or VS field in a VA, VX, VXR or X form instruction. */
-#define VD VC + 1
-#define VS VD
- { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
-
- /* The SIMM field in a VX form instruction. */
-#define SIMM VD + 1
- { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
-
- /* The UIMM field in a VX form instruction, and TE in Z form. */
-#define UIMM SIMM + 1
-#define TE UIMM
- { 0x1f, 16, NULL, NULL, 0 },
-
- /* The SHB field in a VA form instruction. */
-#define SHB UIMM + 1
- { 0xf, 6, NULL, NULL, 0 },
-
- /* The other UIMM field in a half word EVX form instruction. */
-#define EVUIMM_2 SHB + 1
- { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
-
- /* The other UIMM field in a word EVX form instruction. */
-#define EVUIMM_4 EVUIMM_2 + 1
- { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
-
- /* The other UIMM field in a double EVX form instruction. */
-#define EVUIMM_8 EVUIMM_4 + 1
- { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
-
- /* The WS field. */
-#define WS EVUIMM_8 + 1
- { 0x7, 11, NULL, NULL, 0 },
-
- /* The L field in an mtmsrd or A form instruction or W in an X form. */
-#define A_L WS + 1
-#define W A_L
- { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
-#define RMC A_L + 1
- { 0x3, 9, NULL, NULL, 0 },
-
-#define R RMC + 1
- { 0x1, 16, NULL, NULL, 0 },
-
-#define SP R + 1
- { 0x3, 19, NULL, NULL, 0 },
-
-#define S SP + 1
- { 0x1, 20, NULL, NULL, 0 },
-
- /* SH field starting at bit position 16. */
-#define SH16 S + 1
- /* The DCM and DGM fields in a Z form instruction. */
-#define DCM SH16
-#define DGM DCM
- { 0x3f, 10, NULL, NULL, 0 },
-
- /* The EH field in larx instruction. */
-#define EH SH16 + 1
- { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
-
- /* The L field in an mtfsf or XFL form instruction. */
-#define XFL_L EH + 1
- { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
-};
-
-const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
- / sizeof (powerpc_operands[0]));
-
-/* The functions used to insert and extract complicated operands. */
-
-/* The BA field in an XL form instruction when it must be the same as
- the BT field in the same instruction. This operand is marked FAKE.
- The insertion function just copies the BT field into the BA field,
- and the extraction function just checks that the fields are the
- same. */
-
-static unsigned long
-insert_bat (unsigned long insn,
- long value ATTRIBUTE_UNUSED,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (((insn >> 21) & 0x1f) << 16);
-}
-
-static long
-extract_bat (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
- *invalid = 1;
- return 0;
-}
-
-/* The BB field in an XL form instruction when it must be the same as
- the BA field in the same instruction. This operand is marked FAKE.
- The insertion function just copies the BA field into the BB field,
- and the extraction function just checks that the fields are the
- same. */
-
-static unsigned long
-insert_bba (unsigned long insn,
- long value ATTRIBUTE_UNUSED,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (((insn >> 16) & 0x1f) << 11);
-}
-
-static long
-extract_bba (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
- *invalid = 1;
- return 0;
-}
-
-/* The BD field in a B form instruction when the - modifier is used.
- This modifier means that the branch is not expected to be taken.
- For chips built to versions of the architecture prior to version 2
- (ie. not Power4 compatible), we set the y bit of the BO field to 1
- if the offset is negative. When extracting, we require that the y
- bit be 1 and that the offset be positive, since if the y bit is 0
- we just want to print the normal form of the instruction.
- Power4 compatible targets use two bits, "a", and "t", instead of
- the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
- "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
- in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
- for branch on CTR. We only handle the taken/not-taken hint here.
- Note that we don't relax the conditions tested here when
- disassembling with -Many because insns using extract_bdm and
- extract_bdp always occur in pairs. One or the other will always
- be valid. */
-
-static unsigned long
-insert_bdm (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if ((value & 0x8000) != 0)
- insn |= 1 << 21;
- }
- else
- {
- if ((insn & (0x14 << 21)) == (0x04 << 21))
- insn |= 0x02 << 21;
- else if ((insn & (0x14 << 21)) == (0x10 << 21))
- insn |= 0x08 << 21;
- }
- return insn | (value & 0xfffc);
-}
-
-static long
-extract_bdm (unsigned long insn,
- int dialect,
- int *invalid)
-{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
- *invalid = 1;
- }
- else
- {
- if ((insn & (0x17 << 21)) != (0x06 << 21)
- && (insn & (0x1d << 21)) != (0x18 << 21))
- *invalid = 1;
- }
-
- return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
-}
-
-/* The BD field in a B form instruction when the + modifier is used.
- This is like BDM, above, except that the branch is expected to be
- taken. */
-
-static unsigned long
-insert_bdp (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if ((value & 0x8000) == 0)
- insn |= 1 << 21;
- }
- else
- {
- if ((insn & (0x14 << 21)) == (0x04 << 21))
- insn |= 0x03 << 21;
- else if ((insn & (0x14 << 21)) == (0x10 << 21))
- insn |= 0x09 << 21;
- }
- return insn | (value & 0xfffc);
-}
-
-static long
-extract_bdp (unsigned long insn,
- int dialect,
- int *invalid)
-{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
- *invalid = 1;
- }
- else
- {
- if ((insn & (0x17 << 21)) != (0x07 << 21)
- && (insn & (0x1d << 21)) != (0x19 << 21))
- *invalid = 1;
- }
-
- return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
-}
-
-/* Check for legal values of a BO field. */
-
-static int
-valid_bo (long value, int dialect, int extract)
-{
- if ((dialect & PPC_OPCODE_POWER4) == 0)
- {
- int valid;
- /* Certain encodings have bits that are required to be zero.
- These are (z must be zero, y may be anything):
- 001zy
- 011zy
- 1z00y
- 1z01y
- 1z1zz
- */
- switch (value & 0x14)
- {
- default:
- case 0:
- valid = 1;
- break;
- case 0x4:
- valid = (value & 0x2) == 0;
- break;
- case 0x10:
- valid = (value & 0x8) == 0;
- break;
- case 0x14:
- valid = value == 0x14;
- break;
- }
- /* When disassembling with -Many, accept power4 encodings too. */
- if (valid
- || (dialect & PPC_OPCODE_ANY) == 0
- || !extract)
- return valid;
- }
-
- /* Certain encodings have bits that are required to be zero.
- These are (z must be zero, a & t may be anything):
- 0000z
- 0001z
- 0100z
- 0101z
- 001at
- 011at
- 1a00t
- 1a01t
- 1z1zz
- */
- if ((value & 0x14) == 0)
- return (value & 0x1) == 0;
- else if ((value & 0x14) == 0x14)
- return value == 0x14;
- else
- return 1;
-}
-
-/* The BO field in a B form instruction. Warn about attempts to set
- the field to an illegal value. */
-
-static unsigned long
-insert_bo (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg)
-{
- if (!valid_bo (value, dialect, 0))
- *errmsg = "invalid conditional option";
- return insn | ((value & 0x1f) << 21);
-}
-
-static long
-extract_bo (unsigned long insn,
- int dialect,
- int *invalid)
-{
- long value;
-
- value = (insn >> 21) & 0x1f;
- if (!valid_bo (value, dialect, 1))
- *invalid = 1;
- return value;
-}
-
-/* The BO field in a B form instruction when the + or - modifier is
- used. This is like the BO field, but it must be even. When
- extracting it, we force it to be even. */
-
-static unsigned long
-insert_boe (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg)
-{
- if (!valid_bo (value, dialect, 0))
- *errmsg = "invalid conditional option";
- else if ((value & 1) != 0)
- *errmsg = "attempt to set y bit when using + or - modifier";
-
- return insn | ((value & 0x1f) << 21);
-}
-
-static long
-extract_boe (unsigned long insn,
- int dialect,
- int *invalid)
-{
- long value;
-
- value = (insn >> 21) & 0x1f;
- if (!valid_bo (value, dialect, 1))
- *invalid = 1;
- return value & 0x1e;
-}
-
-/* FXM mask in mfcr and mtcrf instructions. */
-
-static unsigned long
-insert_fxm (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg)
-{
- /* If we're handling the mfocrf and mtocrf insns ensure that exactly
- one bit of the mask field is set. */
- if ((insn & (1 << 20)) != 0)
- {
- if (value == 0 || (value & -value) != value)
- {
- *errmsg = "invalid mask field";
- value = 0;
- }
- }
-
- /* If the optional field on mfcr is missing that means we want to use
- the old form of the instruction that moves the whole cr. In that
- case we'll have VALUE zero. There doesn't seem to be a way to
- distinguish this from the case where someone writes mfcr %r3,0. */
- else if (value == 0)
- ;
-
- /* If only one bit of the FXM field is set, we can use the new form
- of the instruction, which is faster. Unlike the Power4 branch hint
- encoding, this is not backward compatible. Do not generate the
- new form unless -mpower4 has been given, or -many and the two
- operand form of mfcr was used. */
- else if ((value & -value) == value
- && ((dialect & PPC_OPCODE_POWER4) != 0
- || ((dialect & PPC_OPCODE_ANY) != 0
- && (insn & (0x3ff << 1)) == 19 << 1)))
- insn |= 1 << 20;
-
- /* Any other value on mfcr is an error. */
- else if ((insn & (0x3ff << 1)) == 19 << 1)
- {
- *errmsg = "ignoring invalid mfcr mask";
- value = 0;
- }
-
- return insn | ((value & 0xff) << 12);
-}
-
-static long
-extract_fxm (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- long mask = (insn >> 12) & 0xff;
-
- /* Is this a Power4 insn? */
- if ((insn & (1 << 20)) != 0)
- {
- /* Exactly one bit of MASK should be set. */
- if (mask == 0 || (mask & -mask) != mask)
- *invalid = 1;
- }
-
- /* Check that non-power4 form of mfcr has a zero MASK. */
- else if ((insn & (0x3ff << 1)) == 19 << 1)
- {
- if (mask != 0)
- *invalid = 1;
- }
-
- return mask;
-}
-
-/* The MB and ME fields in an M form instruction expressed as a single
- operand which is itself a bitmask. The extraction function always
- marks it as invalid, since we never want to recognize an
- instruction which uses a field of this type. */
-
-static unsigned long
-insert_mbe (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- unsigned long uval, mask;
- int mb, me, mx, count, last;
-
- uval = value;
-
- if (uval == 0)
- {
- *errmsg = "illegal bitmask";
- return insn;
- }
-
- mb = 0;
- me = 32;
- if ((uval & 1) != 0)
- last = 1;
- else
- last = 0;
- count = 0;
-
- /* mb: location of last 0->1 transition */
- /* me: location of last 1->0 transition */
- /* count: # transitions */
-
- for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
- {
- if ((uval & mask) && !last)
- {
- ++count;
- mb = mx;
- last = 1;
- }
- else if (!(uval & mask) && last)
- {
- ++count;
- me = mx;
- last = 0;
- }
- }
- if (me == 0)
- me = 32;
-
- if (count != 2 && (count != 0 || ! last))
- *errmsg = "illegal bitmask";
-
- return insn | (mb << 6) | ((me - 1) << 1);
-}
-
-static long
-extract_mbe (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- long ret;
- int mb, me;
- int i;
-
- *invalid = 1;
-
- mb = (insn >> 6) & 0x1f;
- me = (insn >> 1) & 0x1f;
- if (mb < me + 1)
- {
- ret = 0;
- for (i = mb; i <= me; i++)
- ret |= 1L << (31 - i);
- }
- else if (mb == me + 1)
- ret = ~0;
- else /* (mb > me + 1) */
- {
- ret = ~0;
- for (i = me + 1; i < mb; i++)
- ret &= ~(1L << (31 - i));
- }
- return ret;
-}
-
-/* The MB or ME field in an MD or MDS form instruction. The high bit
- is wrapped to the low end. */
-
-static unsigned long
-insert_mb6 (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x1f) << 6) | (value & 0x20);
-}
-
-static long
-extract_mb6 (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 6) & 0x1f) | (insn & 0x20);
-}
-
-/* The NB field in an X form instruction. The value 32 is stored as
- 0. */
-
-static long
-extract_nb (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- long ret;
-
- ret = (insn >> 11) & 0x1f;
- if (ret == 0)
- ret = 32;
- return ret;
-}
-
-/* The NSI field in a D form instruction. This is the same as the SI
- field, only negated. The extraction function always marks it as
- invalid, since we never want to recognize an instruction which uses
- a field of this type. */
-
-static unsigned long
-insert_nsi (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (-value & 0xffff);
-}
-
-static long
-extract_nsi (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- *invalid = 1;
- return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
-}
-
-/* The RA field in a D or X form instruction which is an updating
- load, which means that the RA field may not be zero and may not
- equal the RT field. */
-
-static unsigned long
-insert_ral (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (value == 0
- || (unsigned long) value == ((insn >> 21) & 0x1f))
- *errmsg = "invalid register operand when updating";
- return insn | ((value & 0x1f) << 16);
-}
-
-/* The RA field in an lmw instruction, which has special value
- restrictions. */
-
-static unsigned long
-insert_ram (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if ((unsigned long) value >= ((insn >> 21) & 0x1f))
- *errmsg = "index register in load range";
- return insn | ((value & 0x1f) << 16);
-}
-
-/* The RA field in the DQ form lq instruction, which has special
- value restrictions. */
-
-static unsigned long
-insert_raq (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- long rtvalue = (insn & RT_MASK) >> 21;
-
- if (value == rtvalue)
- *errmsg = "source and target register operands must be different";
- return insn | ((value & 0x1f) << 16);
-}
-
-/* The RA field in a D or X form instruction which is an updating
- store or an updating floating point load, which means that the RA
- field may not be zero. */
-
-static unsigned long
-insert_ras (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg)
-{
- if (value == 0)
- *errmsg = "invalid register operand when updating";
- return insn | ((value & 0x1f) << 16);
-}
-
-/* The RB field in an X form instruction when it must be the same as
- the RS field in the instruction. This is used for extended
- mnemonics like mr. This operand is marked FAKE. The insertion
- function just copies the BT field into the BA field, and the
- extraction function just checks that the fields are the same. */
-
-static unsigned long
-insert_rbs (unsigned long insn,
- long value ATTRIBUTE_UNUSED,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | (((insn >> 21) & 0x1f) << 11);
-}
-
-static long
-extract_rbs (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid)
-{
- if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
- *invalid = 1;
- return 0;
-}
-
-/* The SH field in an MD form instruction. This is split. */
-
-static unsigned long
-insert_sh6 (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
-}
-
-static long
-extract_sh6 (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
-}
-
-/* The SPR field in an XFX form instruction. This is flipped--the
- lower 5 bits are stored in the upper 5 and vice- versa. */
-
-static unsigned long
-insert_spr (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
-}
-
-static long
-extract_spr (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
-}
-
-/* Some dialects have 8 SPRG registers instead of the standard 4. */
-
-static unsigned long
-insert_sprg (unsigned long insn,
- long value,
- int dialect,
- const char **errmsg)
-{
- /* This check uses PPC_OPCODE_403 because PPC405 is later defined
- as a synonym. If ever a 405 specific dialect is added this
- check should use that instead. */
- if (value > 7
- || (value > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
- *errmsg = "invalid sprg number";
-
- /* If this is mfsprg4..7 then use spr 260..263 which can be read in
- user mode. Anything else must use spr 272..279. */
- if (value <= 3 || (insn & 0x100) != 0)
- value |= 0x10;
-
- return insn | ((value & 0x17) << 16);
-}
-
-static long
-extract_sprg (unsigned long insn,
- int dialect,
- int *invalid)
-{
- unsigned long val = (insn >> 16) & 0x1f;
-
- /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
- If not BOOKE or 405, then both use only 272..275. */
- if (val <= 3
- || (val < 0x10 && (insn & 0x100) != 0)
- || (val - 0x10 > 3
- && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
- *invalid = 1;
- return val & 7;
-}
-
-/* The TBR field in an XFX instruction. This is just like SPR, but it
- is optional. When TBR is omitted, it must be inserted as 268 (the
- magic number of the TB register). These functions treat 0
- (indicating an omitted optional operand) as 268. This means that
- ``mftb 4,0'' is not handled correctly. This does not matter very
- much, since the architecture manual does not define mftb as
- accepting any values other than 268 or 269. */
-
-#define TB (268)
-
-static unsigned long
-insert_tbr (unsigned long insn,
- long value,
- int dialect ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
-{
- if (value == 0)
- value = TB;
- return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
-}
-
-static long
-extract_tbr (unsigned long insn,
- int dialect ATTRIBUTE_UNUSED,
- int *invalid ATTRIBUTE_UNUSED)
-{
- long ret;
-
- ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
- if (ret == TB)
- ret = 0;
- return ret;
-}
-
-/* Macros used to form opcodes. */
-
-/* The main opcode. */
-#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
-#define OP_MASK OP (0x3f)
-
-/* The main opcode combined with a trap code in the TO field of a D
- form instruction. Used for extended mnemonics for the trap
- instructions. */
-#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
-#define OPTO_MASK (OP_MASK | TO_MASK)
-
-/* The main opcode combined with a comparison size bit in the L field
- of a D form or X form instruction. Used for extended mnemonics for
- the comparison instructions. */
-#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
-#define OPL_MASK OPL (0x3f,1)
-
-/* An A form instruction. */
-#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
-#define A_MASK A (0x3f, 0x1f, 1)
-
-/* An A_MASK with the FRB field fixed. */
-#define AFRB_MASK (A_MASK | FRB_MASK)
-
-/* An A_MASK with the FRC field fixed. */
-#define AFRC_MASK (A_MASK | FRC_MASK)
-
-/* An A_MASK with the FRA and FRC fields fixed. */
-#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
-
-/* An AFRAFRC_MASK, but with L bit clear. */
-#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
-
-/* A B form instruction. */
-#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
-#define B_MASK B (0x3f, 1, 1)
-
-/* A B form instruction setting the BO field. */
-#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
-#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
-
-/* A BBO_MASK with the y bit of the BO field removed. This permits
- matching a conditional branch regardless of the setting of the y
- bit. Similarly for the 'at' bits used for power4 branch hints. */
-#define Y_MASK (((unsigned long) 1) << 21)
-#define AT1_MASK (((unsigned long) 3) << 21)
-#define AT2_MASK (((unsigned long) 9) << 21)
-#define BBOY_MASK (BBO_MASK &~ Y_MASK)
-#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
-
-/* A B form instruction setting the BO field and the condition bits of
- the BI field. */
-#define BBOCB(op, bo, cb, aa, lk) \
- (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
-#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
-
-/* A BBOCB_MASK with the y bit of the BO field removed. */
-#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
-#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
-#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
-
-/* A BBOYCB_MASK in which the BI field is fixed. */
-#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
-#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
-
-/* A Context form instruction. */
-#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
-#define CTX_MASK CTX(0x3f, 0x7)
-
-/* A User Context form instruction. */
-#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
-#define UCTX_MASK UCTX(0x3f, 0x1f)
-
-/* The main opcode mask with the RA field clear. */
-#define DRA_MASK (OP_MASK | RA_MASK)
-
-/* A DS form instruction. */
-#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
-#define DS_MASK DSO (0x3f, 3)
-
-/* A DE form instruction. */
-#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
-#define DE_MASK DEO (0x3e, 0xf)
-
-/* An EVSEL form instruction. */
-#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
-#define EVSEL_MASK EVSEL(0x3f, 0xff)
-
-/* An M form instruction. */
-#define M(op, rc) (OP (op) | ((rc) & 1))
-#define M_MASK M (0x3f, 1)
-
-/* An M form instruction with the ME field specified. */
-#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
-
-/* An M_MASK with the MB and ME fields fixed. */
-#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
-
-/* An M_MASK with the SH and ME fields fixed. */
-#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
-
-/* An MD form instruction. */
-#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
-#define MD_MASK MD (0x3f, 0x7, 1)
-
-/* An MD_MASK with the MB field fixed. */
-#define MDMB_MASK (MD_MASK | MB6_MASK)
-
-/* An MD_MASK with the SH field fixed. */
-#define MDSH_MASK (MD_MASK | SH6_MASK)
-
-/* An MDS form instruction. */
-#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
-#define MDS_MASK MDS (0x3f, 0xf, 1)
-
-/* An MDS_MASK with the MB field fixed. */
-#define MDSMB_MASK (MDS_MASK | MB6_MASK)
-
-/* An SC form instruction. */
-#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
-#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
-
-/* A VX form instruction. */
-#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
-
-/* The mask for an VX form instruction. */
-#define VX_MASK VX(0x3f, 0x7ff)
-
-/* A VA form instruction. */
-#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
-
-/* The mask for a VA form instruction. */
-#define VXA_MASK VXA(0x3f, 0x3f)
-
-/* A VXR form instruction. */
-#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
-
-/* The mask for a VXR form instruction. */
-#define VXR_MASK VXR(0x3f, 0x3ff, 1)
-
-/* An X form instruction. */
-#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
-
-/* A Z form instruction. */
-#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
-
-/* An X form instruction with the RC bit specified. */
-#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
-
-/* A Z form instruction with the RC bit specified. */
-#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
-
-/* The mask for an X form instruction. */
-#define X_MASK XRC (0x3f, 0x3ff, 1)
-
-/* The mask for a Z form instruction. */
-#define Z_MASK ZRC (0x3f, 0x1ff, 1)
-#define Z2_MASK ZRC (0x3f, 0xff, 1)
-
-/* An X_MASK with the RA field fixed. */
-#define XRA_MASK (X_MASK | RA_MASK)
-
-/* An XRA_MASK with the W field clear. */
-#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
-
-/* An X_MASK with the RB field fixed. */
-#define XRB_MASK (X_MASK | RB_MASK)
-
-/* An X_MASK with the RT field fixed. */
-#define XRT_MASK (X_MASK | RT_MASK)
-
-/* An XRT_MASK mask with the L bits clear. */
-#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
-
-/* An X_MASK with the RA and RB fields fixed. */
-#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
-
-/* An X form instruction with the RA field fixed. */
-#define XRA(op, xop, ra) (X((op), (xop)) | (((ra) << 16) & XRA_MASK))
-
-/* An XRARB_MASK, but with the L bit clear. */
-#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
-
-/* An X_MASK with the RT and RA fields fixed. */
-#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
-
-/* An XRTRA_MASK, but with L bit clear. */
-#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
-
-/* An X form instruction with the L bit specified. */
-#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
-
-/* The mask for an X form comparison instruction. */
-#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
-
-/* The mask for an X form comparison instruction with the L field
- fixed. */
-#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
-
-/* An X form trap instruction with the TO field specified. */
-#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
-#define XTO_MASK (X_MASK | TO_MASK)
-
-/* An X form tlb instruction with the SH field specified. */
-#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
-#define XTLB_MASK (X_MASK | SH_MASK)
-
-/* An X form sync instruction. */
-#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
-
-/* An X form sync instruction with everything filled in except the LS field. */
-#define XSYNC_MASK (0xff9fffff)
-
-/* An X_MASK, but with the EH bit clear. */
-#define XEH_MASK (X_MASK & ~((unsigned long )1))
-
-/* An X form AltiVec dss instruction. */
-#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
-#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
-
-/* An XFL form instruction. */
-#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
-#define XFL_MASK XFL (0x3f, 0x3ff, 1)
-
-/* An X form isel instruction. */
-#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
-#define XISEL_MASK XISEL(0x3f, 0x1f)
-
-/* An XL form instruction with the LK field set to 0. */
-#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
-
-/* An XL form instruction which uses the LK field. */
-#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
-
-/* The mask for an XL form instruction. */
-#define XL_MASK XLLK (0x3f, 0x3ff, 1)
-
-/* An XL form instruction which explicitly sets the BO field. */
-#define XLO(op, bo, xop, lk) \
- (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
-#define XLO_MASK (XL_MASK | BO_MASK)
-
-/* An XL form instruction which explicitly sets the y bit of the BO
- field. */
-#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
-#define XLYLK_MASK (XL_MASK | Y_MASK)
-
-/* An XL form instruction which sets the BO field and the condition
- bits of the BI field. */
-#define XLOCB(op, bo, cb, xop, lk) \
- (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
-#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
-
-/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
-#define XLBB_MASK (XL_MASK | BB_MASK)
-#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
-#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
-
-/* A mask for branch instructions using the BH field. */
-#define XLBH_MASK (XL_MASK | (0x1c << 11))
-
-/* An XL_MASK with the BO and BB fields fixed. */
-#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
-
-/* An XL_MASK with the BO, BI and BB fields fixed. */
-#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
-
-/* An XO form instruction. */
-#define XO(op, xop, oe, rc) \
- (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
-#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
-
-/* An XO_MASK with the RB field fixed. */
-#define XORB_MASK (XO_MASK | RB_MASK)
-
-/* An XS form instruction. */
-#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
-#define XS_MASK XS (0x3f, 0x1ff, 1)
-
-/* A mask for the FXM version of an XFX form instruction. */
-#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
-
-/* An XFX form instruction with the FXM field filled in. */
-#define XFXM(op, xop, fxm, p4) \
- (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
- | ((unsigned long)(p4) << 20))
-
-/* An XFX form instruction with the SPR field filled in. */
-#define XSPR(op, xop, spr) \
- (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
-#define XSPR_MASK (X_MASK | SPR_MASK)
-
-/* An XFX form instruction with the SPR field filled in except for the
- SPRBAT field. */
-#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
-
-/* An XFX form instruction with the SPR field filled in except for the
- SPRG field. */
-#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
-
-/* An X form instruction with everything filled in except the E field. */
-#define XE_MASK (0xffff7fff)
-
-/* An X form user context instruction. */
-#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
-#define XUC_MASK XUC(0x3f, 0x1f)
-
-/* The BO encodings used in extended conditional branch mnemonics. */
-#define BODNZF (0x0)
-#define BODNZFP (0x1)
-#define BODZF (0x2)
-#define BODZFP (0x3)
-#define BODNZT (0x8)
-#define BODNZTP (0x9)
-#define BODZT (0xa)
-#define BODZTP (0xb)
-
-#define BOF (0x4)
-#define BOFP (0x5)
-#define BOFM4 (0x6)
-#define BOFP4 (0x7)
-#define BOT (0xc)
-#define BOTP (0xd)
-#define BOTM4 (0xe)
-#define BOTP4 (0xf)
-
-#define BODNZ (0x10)
-#define BODNZP (0x11)
-#define BODZ (0x12)
-#define BODZP (0x13)
-#define BODNZM4 (0x18)
-#define BODNZP4 (0x19)
-#define BODZM4 (0x1a)
-#define BODZP4 (0x1b)
-
-#define BOU (0x14)
-
-/* The BI condition bit encodings used in extended conditional branch
- mnemonics. */
-#define CBLT (0)
-#define CBGT (1)
-#define CBEQ (2)
-#define CBSO (3)
-
-/* The TO encodings used in extended trap mnemonics. */
-#define TOLGT (0x1)
-#define TOLLT (0x2)
-#define TOEQ (0x4)
-#define TOLGE (0x5)
-#define TOLNL (0x5)
-#define TOLLE (0x6)
-#define TOLNG (0x6)
-#define TOGT (0x8)
-#define TOGE (0xc)
-#define TONL (0xc)
-#define TOLT (0x10)
-#define TOLE (0x14)
-#define TONG (0x14)
-#define TONE (0x18)
-#define TOU (0x1f)
-
-/* Smaller names for the flags so each entry in the opcodes table will
- fit on a single line. */
-#undef PPC
-#define PPC PPC_OPCODE_PPC
-#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
-#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
-#define POWER4 PPC_OPCODE_POWER4
-#define POWER5 PPC_OPCODE_POWER5
-#define POWER6 PPC_OPCODE_POWER6
-/* Documentation purposes only; we don't actually check the isa for disas. */
-#define POWER7 PPC_OPCODE_POWER6
-#define POWER9 PPC_OPCODE_POWER6
-#define CELL PPC_OPCODE_CELL
-#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
-#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
-#define PPC403 PPC_OPCODE_403
-#define PPC405 PPC403
-#define PPC440 PPC_OPCODE_440
-#define PPC750 PPC
-#define PPC860 PPC
-#define PPCVEC PPC_OPCODE_ALTIVEC
-#define POWER PPC_OPCODE_POWER
-#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
-#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
-#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
-#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
-#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
-#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
-#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
-#define MFDEC1 PPC_OPCODE_POWER
-#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
-#define BOOKE PPC_OPCODE_BOOKE
-#define BOOKE64 PPC_OPCODE_BOOKE64
-#define CLASSIC PPC_OPCODE_CLASSIC
-#define PPCE300 PPC_OPCODE_E300
-#define PPCSPE PPC_OPCODE_SPE
-#define PPCISEL PPC_OPCODE_ISEL
-#define PPCEFS PPC_OPCODE_EFS
-#define PPCBRLK PPC_OPCODE_BRLOCK
-#define PPCPMR PPC_OPCODE_PMR
-#define PPCCHLK PPC_OPCODE_CACHELCK
-#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
-#define PPCRFMCI PPC_OPCODE_RFMCI
-
-/* The opcode table.
-
- The format of the opcode table is:
-
- NAME OPCODE MASK FLAGS { OPERANDS }
-
- NAME is the name of the instruction.
- OPCODE is the instruction opcode.
- MASK is the opcode mask; this is used to tell the disassembler
- which bits in the actual opcode must match OPCODE.
- FLAGS are flags indicated what processors support the instruction.
- OPERANDS is the list of operands.
-
- The disassembler reads the table in order and prints the first
- instruction which matches, so this table is sorted to put more
- specific instructions before more general instructions. It is also
- sorted by major opcode. */
-
-const struct powerpc_opcode powerpc_opcodes[] = {
-{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
-{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
-{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
-
-{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
-{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
-{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
-{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
-
-{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
-{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
-{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
-
- /* Double-precision opcodes. */
- /* Some of these conflict with AltiVec, so move them before, since
- PPCVEC includes the PPC_OPCODE_PPC set. */
-{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
-{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
-{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
- /* End of double-precision opcodes. */
-
-{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
-{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
-{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
-{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
-{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
-{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
-{ "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrldnm", VX(4, 453), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} },
-{ "vrlwnm", VX(4, 389), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
-{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
-{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
-{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
-{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
-{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
-{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
-{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
-
-{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
-{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
-{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
-{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
-{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
-{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
-{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
-{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
-{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
-{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
-{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
-
-{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
-{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
-{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
-{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
-{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
-{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
-
-{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
-{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
-{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
-{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
-{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
-{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
-{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
-{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
-{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
-
-{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
-{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
-{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
-{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
-{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
-{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
-{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
-{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
-{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
-{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
-
-{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
-{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
-{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
-{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
-
-{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
-{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
-{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
-{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
-
-{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
-
-{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
-{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
-
-{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
-{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
-
-{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
-{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
-
-{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
-
-{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
-{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
-{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
-{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
-
-{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
-{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
-{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
-{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
-
-{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
-{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
-{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
-{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
-
-{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
-{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
-{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
-
-{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
-{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
-{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
-
-{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
-{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
-{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
-{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
-{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
-{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
-
-{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
-{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
-{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
-{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
-{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
-
-{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
-{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
-{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
-{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
-{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
-{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
-{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
-{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
-{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
-{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
-{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
-{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
-{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
-{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
-{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
-{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
-{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
-{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
-{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
-{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
-{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
-{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
-{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
-{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
-{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
-{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
-{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
-{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
-{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
-{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
-{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
-{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
-{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
-{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
-{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
-{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
-{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
-{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
-{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
-{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
-{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
-{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
-{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
-{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
-{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
-{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
-{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
-{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
-{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
-{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
-{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
-{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
-{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
-
-{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
-{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
-{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
-{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
-{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
-
-{ "b", B(18,0,0), B_MASK, COM, { LI } },
-{ "bl", B(18,0,1), B_MASK, COM, { LI } },
-{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
-{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
-
-{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
-
-{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
-{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
-{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
-{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
-{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
-{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
-{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
-{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
-{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
-{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
-{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
-{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
-{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
-{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
-
-{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
-
-{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
-{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
-{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
-
-{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
-{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
-
-{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
-
-{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
-
-{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
-{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
-
-{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
-{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
-
-{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
-
-{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
-
-{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
-
-{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
-{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
-
-{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
-
-{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
-
-{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
-
-{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
-{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
-
-{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
-{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
-
-{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
-{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
-{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
-{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
-{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
-{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
-{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
-{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
-{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
-{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
-{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
-{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
-{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
-{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
-{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
-
-{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
-{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
-
-{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
-{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
-
-{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
-{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
-{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
-{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
-{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
-{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
-{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
-{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
-
-{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
-{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
-
-{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
-{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
-{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
-{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
-
-{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
-{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
-{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
-{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
-{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
-{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
-
-{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
-{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
-{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
-
-{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
-{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
-{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
-{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
-{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-
-{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
-{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
-
-{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-
-{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
-
-{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
-{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
-{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
-{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
-
-{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
-{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
-
-{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
-{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
-{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
-{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
-
-{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
-{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
-{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
-{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
-{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
-{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
-{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
-{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
-
-{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
-{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
-
-{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-
-{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
-
-{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
-{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
-
-{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
-{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
-{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
-
-{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
-
-{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
-
-{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
-{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
-
-{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
-{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
-{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
-
-{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
-{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
-{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
-{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
-
-{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
-{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
-
-{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
-{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
-{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
-
-{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
-{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
-{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
-{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
-
-{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
-{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
-
-{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
-
-{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
-
-{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
-{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
-
-{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
-{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
-
-{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
-{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
-{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
-{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
-{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
-{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
-{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
-{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
-{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
-{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
-{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
-{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
-{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
-{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
-{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
-{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
-
-{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-
-{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
-
-{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
-{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
-
-{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
-
-{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
-
-{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
-
-{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
-{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
-
-{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
-
-{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
-{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
-{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
-{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
-
-{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
-{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
-
-{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
-
-{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
-
-{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
-
-{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
-{ "popcntw", X(31,378), XRB_MASK, POWER7, { RA, RS } },
-{ "popcntd", X(31,506), XRB_MASK, POWER7, { RA, RS } },
-
-{ "cnttzw", XRC(31,538,0), XRB_MASK, POWER9, { RA, RS } },
-{ "cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, { RA, RS } },
-{ "cnttzd", XRC(31,570,0), XRB_MASK, POWER9, { RA, RS } },
-{ "cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, { RA, RS } },
-
-{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
-{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
-{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
-{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
-
-{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
-
-{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
-
-{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
-
-{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
-{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
-{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
-
-{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
-
-{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
-
-{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
-
-{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
-{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
-
-{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
-{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
-{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
-
-{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
-
-{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
-{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
-
-{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
-
-{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
-
-{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
-{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
-
-{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
-{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
-
-{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
-
-{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
-
-{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
-
-{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
-
-{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
-
-{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
-
-{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
-
-{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
-{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
-{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
-
-{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
-
-{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
-
-{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
-{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
-{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
-
-{ "addex", XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } },
-
-{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
-{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
-{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
-
-{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
-
-{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
-
-{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
-{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
-
-{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
-
-{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
-
-{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
-
-{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
-{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
-
-{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
-{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
-{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
-
-{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
-
-{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
-{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
-
-{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
-
-{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
-
-{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
-{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
-
-{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
-{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
-
-{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
-
-{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
-
-{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
-{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
-
-{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
-{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
-{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
-{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
-{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
-{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
-{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
-{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
-{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
-{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
-{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
-{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
-{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
-{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
-{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
-{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
-{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
-{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
-{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
-{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
-{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
-{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
-{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
-{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
-{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
-{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
-{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
-{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
-
-{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
-{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
-
-{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
-
-{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
-{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
-{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
-{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
-{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
-{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
-{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
-{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
-{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
-{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
-{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
-{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
-{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
-{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
-{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
-{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
-{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
-{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
-{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
-{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
-{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
-{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
-{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
-{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
-{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
-{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
-{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
-{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
-{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
-{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
-{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
-{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
-{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
-{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
-{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
-{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
-{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
-{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
-{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
-{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
-{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
-{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
-{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
-{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
-{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
-{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
-{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
-{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
-{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
-{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
-{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
-{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
-{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
-{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
-{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
-{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
-{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
-{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
-{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
-{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
-{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
-{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
-{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
-{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
-{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
-{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
-{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
-{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
-{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
-{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
-{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
-{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
-{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
-{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
-{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
-{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
-{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
-{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
-{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
-{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
-{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
-{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
-{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
-{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
-{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
-{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
-{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
-{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
-{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
-{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
-{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
-{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
-{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
-{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
-{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
-{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
-{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
-{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
-{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
-{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
-{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
-{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
-{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
-{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
-{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
-{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
-{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
-{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
-{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
-{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
-{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
-{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
-{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
-{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
-{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
-{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
-{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
-{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
-{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
-{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
-{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
-{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
-{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
-{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
-{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
-{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
-{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
-{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
-{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
-{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
-{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
-{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
-{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
-{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
-{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
-{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
-{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
-{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
-{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
-{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
-{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
-{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
-{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
-{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
-{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
-
-{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
-
-{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-
-{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
-
-{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
-
-{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
-
-{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
-{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
-{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
-{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
-
-{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
-{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
-{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
-{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
-
-{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
-
-{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
-
-{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
-
-{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
-
-{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
-
-{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
-
-{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-
-{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
-
-{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
-
-{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
-
-{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
-
-{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
-
-{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
-
-{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
-
-{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
-
-{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
-
-{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
-
-{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
-
-{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
-{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
-{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
-
-{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
-
-{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
-
-{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
-
-{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
-
-{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
-{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
-{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
-{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
-{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
-{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
-{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
-{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
-{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
-{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
-{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
-{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
-{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
-{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
-{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
-{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
-{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
-{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
-{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
-{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
-{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
-{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
-{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
-{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
-{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
-{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
-{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
-{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
-{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
-{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
-{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
-{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
-{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
-{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
-{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
-{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
-{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
-{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
-
-{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
-
-{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
-
-{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
-
-{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
-
-{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
-{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
-{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
-{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
-{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
-{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
-{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
-{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
-{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
-{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
-{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
-{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
-{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
-{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
-{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
-{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
-{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
-{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
-{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
-{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
-{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
-{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
-{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
-{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
-{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
-{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
-{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
-{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
-{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
-{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
-{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
-{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
-{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
-{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
-{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
-{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
-{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
-{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
-{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
-{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
-{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
-{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
-{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
-{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
-{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
-{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
-{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
-{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
-{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
-{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
-{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
-{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
-{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
-{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
-{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
-{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
-{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
-{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
-{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
-{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
-{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
-{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
-{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
-{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
-{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
-{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
-{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
-{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
-{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
-{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
-{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
-{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
-{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
-{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
-{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
-{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
-{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
-{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
-{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
-{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
-{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
-{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
-{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
-{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
-{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
-{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
-{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
-{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
-{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
-{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
-{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
-{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
-{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
-{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
-{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
-{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
-{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
-{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
-{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
-{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
-{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
-{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
-{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
-{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
-{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
-{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
-{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
-{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
-{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
-{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
-{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
-{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
-{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
-{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
-{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
-{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
-{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
-{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
-{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
-{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
-{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
-{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
-{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
-{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
-{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
-{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
-{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
-{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
-
-{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
-
-{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
-{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
-
-{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
-
-{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
-
-{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
-
-{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
-{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
-{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
-{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
-
-{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
-{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
-
-{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
-{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
-
-{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
-{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
-
-{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
-
-{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
-
-{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
-
-{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
-
-{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
-
-{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
-{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
-
-{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
-
-{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
-
-{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
-{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
-{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
-
-{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
-{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
-
-{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
-{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
-{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
-
-{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
-{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
-
-{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
-
-{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
-
-{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
-
-{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
-
-{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
-
-{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
-{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
-
-{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
-{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
-{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
-{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
-{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
-
-{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
-
-{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
-
-{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
-
-{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
-
-{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
-
-{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
-
-{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
-
-{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
-
-{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
-{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
-
-{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
-{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
-
-{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
-
-{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
-{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
-{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
-
-{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
-
-{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
-{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
-
-{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
-
-{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
-{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
-
-{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
-
-{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
-{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
-{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
-
-{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
-
-{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
-
-{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
-
-{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
-{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
-
-{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
-
-{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
-{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
-
-{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
-
-{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
-{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
-{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
-
-{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
-{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
-
-{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
-{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
-
-{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
-
-{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
-
-{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
-{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
-
-{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
-{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
-{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
-{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
-
-{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
-
-{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
-
-{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
-{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
-
-{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
-
-{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
-
-{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
-{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
-{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
-{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
-
-{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
-
-{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
-
-{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
-
-{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
-{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
-{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
-
-{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
-{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
-{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
-{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
-
-{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
-
-{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
-{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
-{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
-
-{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
-
-{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
-{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
-
-{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
-{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
-
-{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
-
-{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
-
-{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
-{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
-{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
-{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
-
-{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
-
-{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
-
-{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
-
-{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
-{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
-
-{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
-
-{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
-{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
-
-{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
-
-{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
-
-{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
-{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
-{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
-
-{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
-
-{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
-{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
-{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
-
-/* New load/store left/right index vector instructions that are in the Cell only. */
-{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
-{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
-{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
-{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
-
-{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
-{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
-
-{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
-{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
-
-{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
-
-{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
-
-{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
-{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
-
-{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
-{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
-
-{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
-
-{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
-
-{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
-
-{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
-
-{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
-
-{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
-
-{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
-
-{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
-
-{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
-{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
-
-{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
-{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
-
-{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
-
-{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
-
-{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
-
-{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
-
-{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
-
-{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
-
-{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
-
-{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
-
-{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
-
-{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
-
-{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
-
-{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
-
-{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
-{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
-{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
-{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
-{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
-{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
-{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
-{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
-{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
-{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
-{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
-{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
-{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
-{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
-
-{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
-
-{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
-
-{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
-
-{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-
-{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-
-{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-
-{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
-
-{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
-{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
-
-{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
-{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
-
-{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
-{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
-
-{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
-{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
-
-{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-
-{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-
-{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-
-{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-
-{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-
-{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-
-{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
-{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
-
-{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-
-{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-
-{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
-{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
-{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
-
-{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-
-{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
-{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
-
-{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
-{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
-{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
-
-{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
-
-{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
-
-{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
-
-{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
-{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
-{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
-{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
-{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
-{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
-{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
-{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
-{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
-{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
-{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
-{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
-
-{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
-
-{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
-
-{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
-
-{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
-
-{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-
-{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
-{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
-
-{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
-{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
-{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
-{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
-
-{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
-{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
-{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
-{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
-
-{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-
-{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-
-{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
-{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
-
-{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
-{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
-
-{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
-
-{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
-{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
-
-{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
-{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
-{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
-{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
-
-{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
-{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
-
-{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-
-{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-
-{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-
-{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
-{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
-
-{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
-
-{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-
-{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
-{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
-
-{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
-{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
-
-{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
-
-{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-
-{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
-{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
-
-{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
-{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
-
-{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
-{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
-
-{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
-
-{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-
-{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
-{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
-
-{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
-{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
-
-{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
-{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
-{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
-
-{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
-
-{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
-{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
-
-{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
-{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
-
-{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
-{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
-{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
-{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
-{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
-{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
-{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
-{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
-
-{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-{ "mffsl", XRA(63,583,12), XRARB_MASK, POWER9, { FRT } },
-
-{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
-{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
-
-{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
-
-{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
-{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
-
-{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
-{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
-{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
-
-{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
-{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
-
-{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
-{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
-
-{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
-{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
-
-{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
-{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
-
-{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
-{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
-
-};
-
-const int powerpc_num_opcodes =
- sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
-
-/* The macro table. This is only used by the assembler. */
-
-/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
- when x=0; 32-x when x is between 1 and 31; are negative if x is
- negative; and are 32 or more otherwise. This is what you want
- when, for instance, you are emulating a right shift by a
- rotate-left-and-mask, because the underlying instructions support
- shifts of size 0 but not shifts of size 32. By comparison, when
- extracting x bits from some word you want to use just 32-x, because
- the underlying instructions don't support extracting 0 bits but do
- support extracting the whole word (32 bits in this case). */
-
-const struct powerpc_macro powerpc_macros[] = {
-{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
-{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
-{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
-{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
-{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
-{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
-{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
-{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
-{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
-{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
-{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
-{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
-{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
-{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
-{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
-{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
-
-{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
-{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
-{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
-{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
-{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
-{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
-{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
-{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
-{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
-{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
-{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
-{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
-{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
-{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
-{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
-{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
-{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
-{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
-{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
-{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
-};
-
-const int powerpc_num_macros =
- sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
-
-
-/* This file provides several disassembler functions, all of which use
- the disassembler interface defined in dis-asm.h. Several functions
- are provided because this file handles disassembly for the PowerPC
- in both big and little endian mode and also for the POWER (RS/6000)
- chip. */
-
-static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
-
-/* Determine which set of machines to disassemble for. PPC403/601 or
- BookE. For convenience, also disassemble instructions supported
- by the AltiVec vector unit. */
-
-static int
-powerpc_dialect (struct disassemble_info *info)
-{
- int dialect = PPC_OPCODE_PPC;
-
- if (BFD_DEFAULT_TARGET_SIZE == 64)
- dialect |= PPC_OPCODE_64;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "booke") != NULL)
- dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
- else if ((info->mach == bfd_mach_ppc_e500)
- || (info->disassembler_options
- && strstr (info->disassembler_options, "e500") != NULL))
- dialect |= (PPC_OPCODE_BOOKE
- | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
- | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
- | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
- | PPC_OPCODE_RFMCI);
- else if (info->disassembler_options
- && strstr (info->disassembler_options, "efs") != NULL)
- dialect |= PPC_OPCODE_EFS;
- else if (info->disassembler_options
- && strstr (info->disassembler_options, "e300") != NULL)
- dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
- else if (info->disassembler_options
- && strstr (info->disassembler_options, "440") != NULL)
- dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
- | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
- else
- dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
- | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "power4") != NULL)
- dialect |= PPC_OPCODE_POWER4;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "power5") != NULL)
- dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "cell") != NULL)
- dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "power6") != NULL)
- dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
-
- if (info->disassembler_options
- && strstr (info->disassembler_options, "any") != NULL)
- dialect |= PPC_OPCODE_ANY;
-
- if (info->disassembler_options)
- {
- if (strstr (info->disassembler_options, "32") != NULL)
- dialect &= ~PPC_OPCODE_64;
- else if (strstr (info->disassembler_options, "64") != NULL)
- dialect |= PPC_OPCODE_64;
- }
-
- info->private_data = (char *) 0 + dialect;
- return dialect;
-}
-
-/* QEMU default */
-int
-print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
-{
- int dialect = (char *) info->private_data - (char *) 0;
- return print_insn_powerpc (memaddr, info, info->endian == BFD_ENDIAN_BIG,
- dialect);
-}
-
-/* Print a big endian PowerPC instruction. */
-
-int
-print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
-{
- int dialect = (char *) info->private_data - (char *) 0;
- return print_insn_powerpc (memaddr, info, 1, dialect);
-}
-
-/* Print a little endian PowerPC instruction. */
-
-int
-print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
-{
- int dialect = (char *) info->private_data - (char *) 0;
- return print_insn_powerpc (memaddr, info, 0, dialect);
-}
-
-/* Print a POWER (RS/6000) instruction. */
-
-int
-print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
-{
- return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
-}
-
-/* Extract the operand value from the PowerPC or POWER instruction. */
-
-static long
-operand_value_powerpc (const struct powerpc_operand *operand,
- unsigned long insn, int dialect)
-{
- long value;
- int invalid;
- /* Extract the value from the instruction. */
- if (operand->extract)
- value = (*operand->extract) (insn, dialect, &invalid);
- else
- {
- value = (insn >> operand->shift) & operand->bitm;
- if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
- {
- /* BITM is always some number of zeros followed by some
- number of ones, followed by some number of zeros. */
- unsigned long top = operand->bitm;
- /* top & -top gives the rightmost 1 bit, so this
- fills in any trailing zeros. */
- top |= (top & -top) - 1;
- top &= ~(top >> 1);
- value = (value ^ top) - top;
- }
- }
-
- return value;
-}
-
-/* Determine whether the optional operand(s) should be printed. */
-
-static int
-skip_optional_operands (const unsigned char *opindex,
- unsigned long insn, int dialect)
-{
- const struct powerpc_operand *operand;
-
- for (; *opindex != 0; opindex++)
- {
- operand = &powerpc_operands[*opindex];
- if ((operand->flags & PPC_OPERAND_NEXT) != 0
- || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
- && operand_value_powerpc (operand, insn, dialect) != 0))
- return 0;
- }
-
- return 1;
-}
-
-/* Print a PowerPC or POWER instruction. */
-
-static int
-print_insn_powerpc (bfd_vma memaddr,
- struct disassemble_info *info,
- int bigendian,
- int dialect)
-{
- bfd_byte buffer[4];
- int status;
- unsigned long insn;
- const struct powerpc_opcode *opcode;
- const struct powerpc_opcode *opcode_end;
- unsigned long op;
-
- if (dialect == 0)
- dialect = powerpc_dialect (info);
-
- status = (*info->read_memory_func) (memaddr, buffer, 4, info);
- if (status != 0)
- {
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
- }
-
- if (bigendian)
- insn = bfd_getb32 (buffer);
- else
- insn = bfd_getl32 (buffer);
-
- /* Get the major opcode of the instruction. */
- op = PPC_OP (insn);
-
- /* Find the first match in the opcode table. We could speed this up
- a bit by doing a binary search on the major opcode. */
- opcode_end = powerpc_opcodes + powerpc_num_opcodes;
- again:
- for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
- {
- unsigned long table_op;
- const unsigned char *opindex;
- const struct powerpc_operand *operand;
- int invalid;
- int need_comma;
- int need_paren;
- int skip_optional;
-
- table_op = PPC_OP (opcode->opcode);
- if (op < table_op)
- break;
- if (op > table_op)
- continue;
-
- if ((insn & opcode->mask) != opcode->opcode
- || (opcode->flags & dialect) == 0)
- continue;
-
- /* Make two passes over the operands. First see if any of them
- have extraction functions, and, if they do, make sure the
- instruction is valid. */
- invalid = 0;
- for (opindex = opcode->operands; *opindex != 0; opindex++)
- {
- operand = powerpc_operands + *opindex;
- if (operand->extract)
- (*operand->extract) (insn, dialect, &invalid);
- }
- if (invalid)
- continue;
-
- /* The instruction is valid. */
- if (opcode->operands[0] != 0)
- (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
- else
- (*info->fprintf_func) (info->stream, "%s", opcode->name);
-
- /* Now extract and print the operands. */
- need_comma = 0;
- need_paren = 0;
- skip_optional = -1;
- for (opindex = opcode->operands; *opindex != 0; opindex++)
- {
- long value;
-
- operand = powerpc_operands + *opindex;
-
- /* Operands that are marked FAKE are simply ignored. We
- already made sure that the extract function considered
- the instruction to be valid. */
- if ((operand->flags & PPC_OPERAND_FAKE) != 0)
- continue;
-
- /* If all of the optional operands have the value zero,
- then don't print any of them. */
- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
- {
- if (skip_optional < 0)
- skip_optional = skip_optional_operands (opindex, insn,
- dialect);
- if (skip_optional)
- continue;
- }
-
- value = operand_value_powerpc (operand, insn, dialect);
-
- if (need_comma)
- {
- (*info->fprintf_func) (info->stream, ",");
- need_comma = 0;
- }
-
- /* Print the operand as directed by the flags. */
- if ((operand->flags & PPC_OPERAND_GPR) != 0
- || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
- (*info->fprintf_func) (info->stream, "r%ld", value);
- else if ((operand->flags & PPC_OPERAND_FPR) != 0)
- (*info->fprintf_func) (info->stream, "f%ld", value);
- else if ((operand->flags & PPC_OPERAND_VR) != 0)
- (*info->fprintf_func) (info->stream, "v%ld", value);
- else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
- (*info->print_address_func) (memaddr + value, info);
- else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
- (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
- else if ((operand->flags & PPC_OPERAND_CR) == 0
- || (dialect & PPC_OPCODE_PPC) == 0)
- (*info->fprintf_func) (info->stream, "%ld", value);
- else
- {
- if (operand->bitm == 7)
- (*info->fprintf_func) (info->stream, "cr%ld", value);
- else
- {
- static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
- int cr;
- int cc;
-
- cr = value >> 2;
- if (cr != 0)
- (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
- cc = value & 3;
- (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
- }
- }
-
- if (need_paren)
- {
- (*info->fprintf_func) (info->stream, ")");
- need_paren = 0;
- }
-
- if ((operand->flags & PPC_OPERAND_PARENS) == 0)
- need_comma = 1;
- else
- {
- (*info->fprintf_func) (info->stream, "(");
- need_paren = 1;
- }
- }
-
- /* We have found and printed an instruction; return. */
- return 4;
- }
-
- if ((dialect & PPC_OPCODE_ANY) != 0)
- {
- dialect = ~PPC_OPCODE_ANY;
- goto again;
- }
-
- /* We could not find a match. */
- (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
-
- return 4;
-}
diff --git a/docs/devel/writing-monitor-commands.rst b/docs/devel/writing-monitor-commands.rst
index 1693822f8f..4aa2bb904d 100644
--- a/docs/devel/writing-monitor-commands.rst
+++ b/docs/devel/writing-monitor-commands.rst
@@ -331,13 +331,10 @@ we should add it to the hmp-commands.hx file::
.cmd = hmp_hello_world,
},
-::
-
- STEXI
- @item hello_world @var{message}
- @findex hello_world
- Print message to the standard output
- ETEXI
+ SRST
+ ``hello_world`` *message*
+ Print message to the standard output
+ ERST
To test this you have to open a user monitor and issue the "hello-world"
command. It might be instructive to check the command's documentation with
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index ae0bc07e75..4d054ca869 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -265,6 +265,7 @@ static void machine_hppa_init(MachineState *machine)
/* Graphics setup. */
if (machine->enable_graphics && vga_interface_type != VGA_NONE) {
+ vga_interface_created = true;
dev = qdev_new("artist");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 0ad1c5fd65..cd5ad3687d 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -166,6 +166,7 @@ bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp)
ISADevice *isa_vga_init(ISABus *bus)
{
+ vga_interface_created = true;
switch (vga_interface_type) {
case VGA_CIRRUS:
return isa_create_simple(bus, "isa-cirrus-vga");
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 7b13098f9b..5ee546f5f6 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -320,6 +320,7 @@ static void mips_fuloong2e_init(MachineState *machine)
/* GPU */
if (vga_interface_type != VGA_NONE) {
+ vga_interface_created = true;
pci_dev = pci_new(-1, "ati-vga");
dev = DEVICE(pci_dev);
qdev_prop_set_uint32(dev, "vgamem_mb", 16);
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index e99417e501..9c58f02853 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2037,6 +2037,7 @@ PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
PCIDevice *pci_vga_init(PCIBus *bus)
{
+ vga_interface_created = true;
switch (vga_interface_type) {
case VGA_CIRRUS:
return pci_create_simple(bus, -1, "cirrus-vga");
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index fe9937e811..8bbae68e1b 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1742,6 +1742,7 @@ static void spapr_rtc_create(SpaprMachineState *spapr)
/* Returns whether we want to use VGA or not */
static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
{
+ vga_interface_created = true;
switch (vga_interface_type) {
case VGA_NONE:
return false;
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index fccaed1eb4..b693eea0e0 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -920,6 +920,7 @@ static void sun4m_hw_init(MachineState *machine)
/* sbus irq 5 */
cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
+ vga_interface_created = true;
} else {
/* If no display specified, default to TCX */
if (graphic_depth != 8 && graphic_depth != 24) {
@@ -935,6 +936,7 @@ static void sun4m_hw_init(MachineState *machine)
tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
+ vga_interface_created = true;
}
}
diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 6fd08e2298..7c461d194a 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -632,6 +632,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
switch (vga_interface_type) {
case VGA_STD:
pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
+ vga_interface_created = true;
break;
case VGA_NONE:
break;
diff --git a/hw/xenpv/xen_machine_pv.c b/hw/xenpv/xen_machine_pv.c
index 8df575a457..20c9611d71 100644
--- a/hw/xenpv/xen_machine_pv.c
+++ b/hw/xenpv/xen_machine_pv.c
@@ -63,6 +63,7 @@ static void xen_init_pv(MachineState *machine)
if (vga_interface_type == VGA_XENFB) {
xen_config_dev_vfb(0, "vnc");
xen_config_dev_vkbd(0);
+ vga_interface_created = true;
}
/* configure disks */
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index aebd23dc20..fc7cb7af5a 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -418,7 +418,6 @@ int print_insn_tci(bfd_vma, disassemble_info*);
int print_insn_big_mips (bfd_vma, disassemble_info*);
int print_insn_little_mips (bfd_vma, disassemble_info*);
int print_insn_nanomips (bfd_vma, disassemble_info*);
-int print_insn_i386 (bfd_vma, disassemble_info*);
int print_insn_m68k (bfd_vma, disassemble_info*);
int print_insn_z8001 (bfd_vma, disassemble_info*);
int print_insn_z8002 (bfd_vma, disassemble_info*);
@@ -429,7 +428,6 @@ int print_insn_h8500 (bfd_vma, disassemble_info*);
int print_insn_arm_a64 (bfd_vma, disassemble_info*);
int print_insn_alpha (bfd_vma, disassemble_info*);
disassembler_ftype arc_get_disassembler (int, int);
-int print_insn_arm (bfd_vma, disassemble_info*);
int print_insn_sparc (bfd_vma, disassemble_info*);
int print_insn_big_a29k (bfd_vma, disassemble_info*);
int print_insn_little_a29k (bfd_vma, disassemble_info*);
@@ -449,7 +447,6 @@ int print_insn_w65 (bfd_vma, disassemble_info*);
int print_insn_d10v (bfd_vma, disassemble_info*);
int print_insn_v850 (bfd_vma, disassemble_info*);
int print_insn_tic30 (bfd_vma, disassemble_info*);
-int print_insn_ppc (bfd_vma, disassemble_info*);
int print_insn_crisv32 (bfd_vma, disassemble_info*);
int print_insn_crisv10 (bfd_vma, disassemble_info*);
int print_insn_microblaze (bfd_vma, disassemble_info*);
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 10e283c170..360a408edf 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -34,6 +34,7 @@ typedef enum {
} VGAInterfaceType;
extern int vga_interface_type;
+extern bool vga_interface_created;
extern int graphic_width;
extern int graphic_height;
diff --git a/qemu-options.hx b/qemu-options.hx
index 5f69b94b8e..796229c433 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -4186,16 +4186,17 @@ SRST
ERST
DEF("xen-domid", HAS_ARG, QEMU_OPTION_xen_domid,
- "-xen-domid id specify xen guest domain id\n", QEMU_ARCH_ALL)
+ "-xen-domid id specify xen guest domain id\n",
+ QEMU_ARCH_ARM | QEMU_ARCH_I386)
DEF("xen-attach", 0, QEMU_OPTION_xen_attach,
"-xen-attach attach to existing xen domain\n"
" libxl will use this when starting QEMU\n",
- QEMU_ARCH_ALL)
+ QEMU_ARCH_ARM | QEMU_ARCH_I386)
DEF("xen-domid-restrict", 0, QEMU_OPTION_xen_domid_restrict,
"-xen-domid-restrict restrict set of available xen operations\n"
" to specified domain id. (Does not affect\n"
" xenpv machine type).\n",
- QEMU_ARCH_ALL)
+ QEMU_ARCH_ARM | QEMU_ARCH_I386)
SRST
``-xen-domid id``
Specify xen guest domain id (XEN only).
diff --git a/scripts/hxtool-conv.pl b/scripts/hxtool-conv.pl
deleted file mode 100755
index eede40b346..0000000000
--- a/scripts/hxtool-conv.pl
+++ /dev/null
@@ -1,137 +0,0 @@
-#!/usr/bin/perl -w
-#
-# Script to convert .hx file STEXI/ETEXI blocks to SRST/ERST
-#
-# Copyright (C) 2020 Linaro
-#
-# This work is licensed under the terms of the GNU GPL, version 2 or
-# (at your option) any later version. See the COPYING file in the
-# top-level directory.
-
-# This script was only ever intended as a one-off conversion operation.
-# Please excuse the places where it is a bit hacky.
-# Some manual intervention after the conversion is expected, as are
-# some warnings from makeinfo.
-# Warning: this script is not idempotent: don't try to run it on
-# a .hx file that already has SRST/ERST sections.
-
-# Expected usage:
-# scripts/hxtool-conv.pl file.hx > file.hx.new
-
-use utf8;
-
-my $reading_texi = 0;
-my $texiblock = '';
-my @tables = ();
-
-sub update_tables($) {
- my ($texi) = @_;
- # Update our list of open table directives: every @table
- # line in the texi fragment is added to the list, and every
- # @end table line means we remove an entry from the list.
- # If this fragment had a completely self contained table with
- # both the @table and @end table lines, this will be a no-op.
- foreach (split(/\n/, $texi)) {
- push @tables, $_ if /^\@table/;
- pop @tables if /^\@end table/;
- }
-}
-
-sub only_table_directives($) {
- # Return true if every line in the fragment is a start or end table directive
- my ($texi) = @_;
- foreach (split(/\n/, $texi)) {
- return 0 unless /^\@table/ or /^\@end table/;
- }
- return 1;
-}
-
-sub output_rstblock($) {
- # Write the output to /tmp/frag.texi, wrapped in whatever current @table
- # lines we need.
- my ($texi) = @_;
-
- # As a special case, if this fragment is only table directives and
- # nothing else, update our set of open table directives but otherwise
- # ignore it. This avoids emitting an empty SRST/ERST block.
- if (only_table_directives($texi)) {
- update_tables($texi);
- return;
- }
-
- open(my $fragfh, '>', '/tmp/frag.texi');
- # First output the currently active set of open table directives
- print $fragfh join("\n", @tables);
- # Next, update our list of open table directives.
- # We need to do this before we emit the closing table directives
- # so that we emit the right number if this fragment had an
- # unbalanced set of directives.
- update_tables($texi);
- # Then emit the texi fragment itself.
- print $fragfh "\n$texi\n";
- # Finally, add the necessary closing table directives.
- print $fragfh "\@end table\n" x scalar @tables;
- close $fragfh;
-
- # Now invoke makeinfo/pandoc on it and slurp the results into a string
- open(my $fh, '-|', "makeinfo --force -o - --docbook "
- . "-D 'qemu_system_x86 QEMU_SYSTEM_X86_MACRO' "
- . "-D 'qemu_system QEMU_SYSTEM_MACRO' /tmp/frag.texi "
- . " | pandoc -f docbook -t rst")
- or die "can't start makeinfo/pandoc: $!";
-
- binmode $fh, ':encoding(utf8)';
-
- print "SRST\n";
-
- # Slurp the whole thing into a string so we can do multiline
- # string matches on it.
- my $rst = do {
- local $/ = undef;
- <$fh>;
- };
- $rst =~ s/^- − /- /gm;
- $rst =~ s/“/"/gm;
- $rst =~ s/”/"/gm;
- $rst =~ s/‘/'/gm;
- $rst =~ s/’/'/gm;
- $rst =~ s/QEMU_SYSTEM_MACRO/|qemu_system|/g;
- $rst =~ s/QEMU_SYSTEM_X86_MACRO/|qemu_system_x86|/g;
- $rst =~ s/(?=::\n\n +\|qemu)/.. parsed-literal/g;
- $rst =~ s/:\n\n::$/::/gm;
-
- # Fix up the invalid reference format makeinfo/pandoc emit:
- # `Some string here <#anchorname>`__
- # should be:
- # :ref:`anchorname`
- $rst =~ s/\`[^<`]+\<\#([^>]+)\>\`__/:ref:`$1`/gm;
- print $rst;
-
- close $fh or die "error on close: $!";
- print "ERST\n";
-}
-
-# Read the whole .hx input file.
-while (<>) {
- # Always print the current line
- print;
- if (/STEXI/) {
- $reading_texi = 1;
- $texiblock = '';
- next;
- }
- if (/ETEXI/) {
- $reading_texi = 0;
- # dump RST version of block
- output_rstblock($texiblock);
- next;
- }
- if ($reading_texi) {
- # Accumulate the texi into a string
- # but drop findex entries as they will confuse makeinfo
- next if /^\@findex/;
- $texiblock .= $_;
- }
-}
-
-die "Unexpectedly still in texi block at EOF" if $reading_texi;
diff --git a/softmmu/globals.c b/softmmu/globals.c
index 3ebd718e35..98b64e0492 100644
--- a/softmmu/globals.c
+++ b/softmmu/globals.c
@@ -40,6 +40,7 @@ int nb_nics;
NICInfo nd_table[MAX_NICS];
int autostart = 1;
int vga_interface_type = VGA_NONE;
+bool vga_interface_created;
Chardev *parallel_hds[MAX_PARALLEL_PORTS];
int win2k_install_hack;
int singlestep;
diff --git a/softmmu/vl.c b/softmmu/vl.c
index c2919579fd..488cc4d09e 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -934,10 +934,12 @@ static const VGAInterfaceInfo vga_interfaces[VGA_TYPE_MAX] = {
.name = "CG3 framebuffer",
.class_names = { "cgthree" },
},
+#ifdef CONFIG_XEN_BACKEND
[VGA_XENFB] = {
.opt_name = "xenfb",
.name = "Xen paravirtualized framebuffer",
},
+#endif
};
static bool vga_interface_available(VGAInterfaceType t)
@@ -1351,6 +1353,7 @@ static void qemu_disable_default_devices(void)
if (!vga_model && !default_vga) {
vga_interface_type = VGA_DEVICE;
+ vga_interface_created = true;
}
if (!has_defaults || machine_class->no_serial) {
default_serial = 0;
@@ -2734,6 +2737,12 @@ static void qemu_machine_creation_done(void)
if (foreach_device_config(DEV_GDB, gdbserver_start) < 0) {
exit(1);
}
+ if (!vga_interface_created && !default_vga &&
+ vga_interface_type != VGA_NONE) {
+ warn_report("A -vga option was passed but this machine "
+ "type does not use that option; "
+ "No VGA device has been created");
+ }
}
void qmp_x_exit_preconfig(Error **errp)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 01176b2569..16fb5f9c12 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -775,12 +775,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
#endif
-static int
-print_insn_thumb1(bfd_vma pc, disassemble_info *info)
-{
- return print_insn_arm(pc | 1, info);
-}
-
static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
{
ARMCPU *ac = ARM_CPU(cpu);
@@ -801,12 +795,10 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
} else {
int cap_mode;
if (env->thumb) {
- info->print_insn = print_insn_thumb1;
info->cap_insn_unit = 2;
info->cap_insn_split = 4;
cap_mode = CS_MODE_THUMB;
} else {
- info->print_insn = print_insn_arm;
info->cap_insn_unit = 4;
info->cap_insn_split = 4;
cap_mode = CS_MODE_ARM;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 99343be926..62c240fa91 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6821,7 +6821,6 @@ static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
: env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
: bfd_mach_i386_i8086);
- info->print_insn = print_insn_i386;
info->cap_arch = CS_ARCH_X86;
info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d4c7813de5..527ad40fcb 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7309,8 +7309,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
info->mach = bfd_mach_ppc;
#endif
}
- info->disassembler_options = (char *)"any";
- info->print_insn = print_insn_ppc;
info->cap_arch = CS_ARCH_PPC;
#ifdef TARGET_PPC64
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index 337fe7c303..dc34b2718b 100755
--- a/tests/vm/openbsd
+++ b/tests/vm/openbsd
@@ -22,8 +22,8 @@ class OpenBSDVM(basevm.BaseVM):
name = "openbsd"
arch = "x86_64"
- link = "https://cdn.openbsd.org/pub/OpenBSD/7.0/amd64/install70.iso"
- csum = "1882f9a23c9800e5dba3dbd2cf0126f552605c915433ef4c5bb672610a4ca3a4"
+ link = "https://cdn.openbsd.org/pub/OpenBSD/7.1/amd64/install71.iso"
+ csum = "d3a7c5b9bf890bc404304a1c96f9ee72e1d9bbcf9cc849c1133bdb0d67843396"
size = "20G"
pkgs = [
# tools
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-15 15:18:42 +0000