diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2021-07-15 18:50:44 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-07-29 10:59:49 +1000 |
| commit | 793abe24aa9c6ad1a06dee091fa4dd4479fef482 (patch) | |
| tree | 2eeb6857ac88505306dcdaa6b93ffcf688033434 | |
| parent | 6ebc0048dd8ff93c2847739599afa630f3d9dabd (diff) | |
i2c/smbus_eeprom: Add feature bit to SPD data
Add the differential clock input feature bit to the generated SPD
data. Most guests don't seem to care but pegasos2 firmware version 1.2
checks for this bit and stops with unsupported module type error if
it's not present. Since this feature is likely present on real memory
modules add it in the general code rather than patching the generated
SPD data in pegasos2 board only.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <19d42ade295d5297aa624a9eb757b8df18cf64d6.1626367844.git.balaton@eik.bme.hu>
Acked-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | hw/i2c/smbus_eeprom.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c index 4d2bf99207..12c5741f38 100644 --- a/hw/i2c/smbus_eeprom.c +++ b/hw/i2c/smbus_eeprom.c @@ -276,7 +276,7 @@ uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size) spd[18] = 12; /* ~CAS latencies supported */ spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */ spd[20] = 2; /* DIMM type / ~WE latencies */ - /* module features */ + spd[21] = (type < DDR2 ? 0x20 : 0); /* module features */ /* memory chip features */ spd[23] = 0x12; /* clock cycle time @ medium CAS latency */ /* data access time */ |