Second RISC-V PR for QEMU 7.1 * Improve device tree generation * Support configuarable marchid, mvendorid, mipid CSR values * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions * Fix incorrect PTE merge in walk_pte * Add TPM support to the virt board # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmJraeUACgkQIeENKd+X # cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok # Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA # d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc # v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35 # VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR # VvnUcI+p73qclCF7LkfL9c//xQT1iA== # =Xkoz # -----END PGP SIGNATURE----- # gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits) hw/riscv: Enable TPM backends hw/riscv: virt: Add device plug support hw/riscv: virt: Add support for generating platform FDT entries hw/riscv: virt: Create a platform bus hw/core: Move the ARM sysbus-fdt to core hw/riscv: virt: Add a machine done notifier target/riscv: add scalar crypto related extenstion strings to isa_string target/riscv: Fix incorrect PTE merge in walk_pte target/riscv: rvk: expose zbk* and zk* properties disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions target/riscv: rvk: add CSR support for Zkr target/riscv: rvk: add support for zksed/zksh extension target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension target/riscv: rvk: add support for sha256 related instructions in zknh extension target/riscv: rvk: add support for zkne/zknd extension in RV64 target/riscv: rvk: add support for zknd/zkne extension in RV32 crypto: move sm4_sbox from target/arm target/riscv: rvk: add support for zbkx extension target/riscv: rvk: add support for zbkc extension ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>