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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-07-27 10:30:08 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-10-17 18:35:49 +0200
commit719f874b83792951faa3fe67378eca4034bec3dc (patch)
tree7c6ab34e66e57df49407d307c5c58e4731953670
parentc148a0572130ff485cd2249fbdd1a3260d5e10a4 (diff)
target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6
Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04, MULT and MULTU opcodes: The value of ac selects an accumulator numbered from 0 to 3. When ac=0, this refers to the original HI/LO register pair of the MIPS32 architecture. In Release 6 of the MIPS Architecture, accumulators are eliminated from MIPS32. Ensure pre-Release 6 is restricted to HI/LO registers pair. Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 4") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-rw-r--r--target/mips/tcg/nanomips_translate.c.inc6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index ccbcecad09..2c022a49f2 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1868,6 +1868,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
+ if (acc || ctx->insn_flags & ISA_MIPS_R6) {
+ check_dsp_r2(ctx);
+ }
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);
@@ -1925,6 +1928,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
+ if (acc || ctx->insn_flags & ISA_MIPS_R6) {
+ check_dsp_r2(ctx);
+ }
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);