diff options
| author | Jules Irenge <jbi.octave@gmail.com> | 2019-04-13 21:28:18 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-05-26 17:44:55 +0200 |
| commit | 9e72f33d854b0a817c0d2fe4bca693b76f0fe776 (patch) | |
| tree | 501ed9fb1bc49aa0fd820e4fc070c6bcf5e44c39 | |
| parent | 8ebf2e1a68408068c0bcd0d02a783fd12f6a9cb5 (diff) | |
target/mips: realign comments to fix checkpatch warnings
Realign comments to fix warnings issued by checkpatc.pl tool
"WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.
Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
| -rw-r--r-- | target/mips/cpu.h | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 71dd403b3b..06a8ed4748 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -37,7 +37,8 @@ union fpr_t { /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ }; -/* define FP_ENDIAN_IDX to access the same location +/* + *define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness */ #if defined(HOST_WORDS_BIGENDIAN) @@ -976,9 +977,11 @@ struct CPUMIPSState { /* TMASK defines different execution modes */ #define MIPS_HFLAG_TMASK 0x1F5807FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ - /* The KSU flags must be the lowest bits in hflags. The flag order - must be the same as defined for CP0 Status. This allows to use - the bits as the value of mmu_idx. */ + /* + * The KSU flags must be the lowest bits in hflags. The flag order + * must be the same as defined for CP0 Status. This allows to use + * the bits as the value of mmu_idx. + */ #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ @@ -988,18 +991,22 @@ struct CPUMIPSState { #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ - /* True if the MIPS IV COP1X instructions can be used. This also - controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S - and RSQRT.D. */ + /* + * True if the MIPS IV COP1X instructions can be used. This also + * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S + * and RSQRT.D. + */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16_SHIFT 10 - /* If translation is interrupted between the branch instruction and + /* + * If translation is interrupted between the branch instruction and * the delay slot, record what type of branch it is so that we can * resume translation properly. It might be possible to reduce - * this from three bits to two. */ + * this from three bits to two. + */ #define MIPS_HFLAG_BMASK_BASE 0x803800 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ @@ -1086,8 +1093,10 @@ void mips_cpu_list(void); extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); -/* MMU modes definitions. We carefully match the indices with our - hflags layout. */ +/* + * MMU modes definitions. We carefully match the indices with our + * hflags layout. + */ #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user @@ -1110,7 +1119,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) #include "exec/cpu-all.h" -/* Memory access type : +/* + * Memory access type : * may be needed for precise access rights control and precise exceptions. */ enum { |