diff options
| author | Stefan Hajnoczi <stefanha@redhat.com> | 2022-11-22 12:19:42 -0500 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2022-11-22 12:19:42 -0500 |
| commit | 80e99f293e22868f50163f98276e0273e0237add (patch) | |
| tree | 2145d6b872d1fad147c2ff9ec6467772ded8bdb3 | |
| parent | 16a550bdc0e49fcda0e6a6c55d648700ad33c8a4 (diff) | |
| parent | 15f8f4671afd22491ce99d28a296514717fead4f (diff) | |
Merge tag 'pull-target-arm-20221122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm:
* Fix broken 5-level pagetable handling
* Fix debug accesses when EL2 is present
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# gpg: Signature made Tue 22 Nov 2022 11:37:44 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221122' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Use signed quantity to represent VMSAv8-64 translation level
target/arm: Don't do two-stage lookup if stage 2 is disabled
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
| -rw-r--r-- | target/arm/ptw.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9a6277d862..f812734bfb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1172,7 +1172,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_secure = ptw->in_secure; - uint32_t level; + int32_t level; ARMVAParameters param; uint64_t ttbr; hwaddr descaddr, indexmask, indexmask_grainsize; @@ -1302,7 +1302,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, */ uint32_t sl0 = extract32(tcr, 6, 2); uint32_t sl2 = extract64(tcr, 33, 1); - uint32_t startlevel; + int32_t startlevel; bool ok; /* SL2 is RES0 unless DS=1 & 4kb granule. */ @@ -2612,8 +2612,8 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + /* If S1 fails, return early. */ + if (ret) { return ret; } @@ -2739,7 +2739,8 @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, * Otherwise, a stage1+stage2 translation is just stage 1. */ ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; - if (arm_feature(env, ARM_FEATURE_EL2)) { + if (arm_feature(env, ARM_FEATURE_EL2) && + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { return get_phys_addr_twostage(env, ptw, address, access_type, result, fi); } |