diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2022-04-01 17:16:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-01 17:16:48 +0100 |
| commit | ea72ac9bc8fcb90405768412ebb9ff01d3b1a2bb (patch) | |
| tree | ff66a61c4496f029974860f62ab50e56921d1fdc | |
| parent | 697d18b1bd2667efa418cc7d7248d5450da547e7 (diff) | |
| parent | a5b1e1ab662aa6dc42d5a913080fccbb8bf82e9b (diff) | |
Merge tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* target/arm: Fix some bugs in secure EL2 handling
* target/arm: Fix assert when !HAVE_CMPXCHG128
* MAINTAINERS: change Fred Konrad's email address
# gpg: Signature made Fri 01 Apr 2022 15:59:59 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20220401' of https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
MAINTAINERS: change Fred Konrad's email address
target/arm: Determine final stage 2 output PA space based on original IPA
target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
target/arm: Fix MTE access checks for disabled SEL2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | .mailmap | 3 | ||||
| -rw-r--r-- | MAINTAINERS | 2 | ||||
| -rw-r--r-- | target/arm/helper.c | 18 | ||||
| -rw-r--r-- | target/arm/internals.h | 2 | ||||
| -rw-r--r-- | target/arm/translate-a64.c | 7 |
5 files changed, 25 insertions, 7 deletions
@@ -56,7 +56,8 @@ Alexander Graf <agraf@csgraf.de> <agraf@suse.de> Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com> Christian Borntraeger <borntraeger@linux.ibm.com> <borntraeger@de.ibm.com> Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com> -Frederic Konrad <konrad@adacore.com> <fred.konrad@greensocs.com> +Frederic Konrad <konrad.frederic@yahoo.fr> <fred.konrad@greensocs.com> +Frederic Konrad <konrad.frederic@yahoo.fr> <konrad@adacore.com> Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com> Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> diff --git a/MAINTAINERS b/MAINTAINERS index cc364afef7..68142340bd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1533,7 +1533,7 @@ F: include/hw/rtc/sun4v-rtc.h Leon3 M: Fabien Chouteau <chouteau@adacore.com> -M: KONRAD Frederic <frederic.konrad@adacore.com> +M: Frederic Konrad <konrad.frederic@yahoo.fr> S: Maintained F: hw/sparc/leon3.c F: hw/*/grlib* diff --git a/target/arm/helper.c b/target/arm/helper.c index 812ca591f4..7d14650615 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7176,7 +7176,7 @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, { int el = arm_current_el(env); - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + if (el < 2 && arm_is_el2_enabled(env)) { uint64_t hcr = arm_hcr_el2_eff(env); if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { return CP_ACCESS_TRAP_EL2; @@ -12644,6 +12644,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, hwaddr ipa; int s2_prot; int ret; + bool ipa_secure; ARMCacheAttrs cacheattrs2 = {}; ARMMMUIdx s2_mmu_idx; bool is_el0; @@ -12657,6 +12658,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + ipa_secure = attrs->secure; + if (arm_is_secure_below_el3(env)) { + if (ipa_secure) { + attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!ipa_secure); + } + s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; @@ -12691,13 +12703,13 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, /* Check if IPA translates to secure or non-secure PA space. */ if (arm_is_secure_below_el3(env)) { - if (attrs->secure) { + if (ipa_secure) { attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); } else { attrs->secure = !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); + || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); } } return 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index a34be2e459..7f696cd36a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1094,7 +1094,7 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, && !(env->cp15.scr_el3 & SCR_ATA)) { return false; } - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + if (el < 2 && arm_is_el2_enabled(env)) { uint64_t hcr = arm_hcr_el2_eff(env); if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { return false; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d1a59fad9c..9333d7be41 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2470,7 +2470,12 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (!HAVE_CMPXCHG128) { gen_helper_exit_atomic(cpu_env); - s->base.is_jmp = DISAS_NORETURN; + /* + * Produce a result so we have a well-formed opcode + * stream when the following (dead) code uses 'tmp'. + * TCG will remove the dead ops for us. + */ + tcg_gen_movi_i64(tmp, 0); } else if (s->be_data == MO_LE) { gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, cpu_exclusive_addr, |