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| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-18 16:00:18 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-18 16:00:18 +0200 |
| commit | dcc65026c4bd8b6fc569b3c1b990fbc8001f8f02 (patch) | |
| tree | d0d1260d7f18f040d6bb56e44d3d741e4fa5ec57 | |
| parent | 98a463171b9a73cd178c6986a83742cbe18375a4 (diff) | |
target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330ed
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-arm/translate.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index d1e1d30248..e56082b26f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -3699,13 +3699,15 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) return 1; nregs = neon_ls_element_type[op].nregs; interleave = neon_ls_element_type[op].interleave; - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); stride = (1 << size) * interleave; for (reg = 0; reg < nregs; reg++) { if (interleave > 2 || (interleave == 2 && nregs == 2)) { - tcg_gen_addi_i32(addr, cpu_R[rn], (1 << size) * reg); + load_reg_var(s, addr, rn); + tcg_gen_addi_i32(addr, addr, (1 << size) * reg); } else if (interleave == 2 && nregs == 4 && reg == 2) { - tcg_gen_addi_i32(addr, cpu_R[rn], 1 << size); + load_reg_var(s, addr, rn); + tcg_gen_addi_i32(addr, addr, 1 << size); } for (pass = 0; pass < 2; pass++) { if (size == 2) { @@ -3777,7 +3779,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) size = (insn >> 6) & 3; nregs = ((insn >> 8) & 3) + 1; stride = (insn & (1 << 5)) ? 2 : 1; - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); for (reg = 0; reg < nregs; reg++) { switch (size) { case 0: @@ -3824,7 +3826,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) abort(); } nregs = ((insn >> 8) & 3) + 1; - tcg_gen_mov_i32(addr, cpu_R[rn]); + load_reg_var(s, addr, rn); for (reg = 0; reg < nregs; reg++) { if (load) { switch (size) { |