diff options
author | Richard Henderson <rth@twiddle.net> | 2011-08-17 14:11:45 -0700 |
---|---|---|
committer | Blue Swirl <blauwirbel@gmail.com> | 2011-08-21 18:52:22 +0000 |
commit | 8399ad59e73a0f48af3edef62f021e2cb6220e12 (patch) | |
tree | bd7382f9e8574f1449cd36a8e00b86e6c3a2842f | |
parent | 4b29ec41c82a6e6c6a50263818e81944ef522fb2 (diff) |
tcg: Add and use TCG_OPF_64BIT.
This allows the simplification of the op_bits function from
tcg/optimize.c.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r-- | tcg/optimize.c | 77 | ||||
-rw-r--r-- | tcg/tcg-opc.h | 98 | ||||
-rw-r--r-- | tcg/tcg.c | 2 | ||||
-rw-r--r-- | tcg/tcg.h | 21 |
4 files changed, 67 insertions, 131 deletions
diff --git a/tcg/optimize.c b/tcg/optimize.c index 7eb5eb1c70..98c7e3f41c 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -92,81 +92,10 @@ static void reset_temp(TCGArg temp, int nb_temps, int nb_globals) } } -static int op_bits(int op) +static int op_bits(enum TCGOpcode op) { - switch (op) { - case INDEX_op_mov_i32: - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_or_i32: - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: -#ifdef TCG_TARGET_HAS_rot_i32 - case INDEX_op_rotl_i32: - case INDEX_op_rotr_i32: -#endif -#ifdef TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: -#endif -#ifdef TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: -#endif -#ifdef TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: -#endif -#ifdef TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: -#endif -#ifdef TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: -#endif - return 32; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_mov_i64: - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_or_i64: - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: -#ifdef TCG_TARGET_HAS_rot_i64 - case INDEX_op_rotl_i64: - case INDEX_op_rotr_i64: -#endif -#ifdef TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: -#endif -#ifdef TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext32s_i64 - case INDEX_op_ext32s_i64: -#endif -#ifdef TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: -#endif -#ifdef TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: -#endif -#ifdef TCG_TARGET_HAS_ext32u_i64 - case INDEX_op_ext32u_i64: -#endif - return 64; -#endif - default: - fprintf(stderr, "Unrecognized operation %d in op_bits.\n", op); - tcg_abort(); - } + const TCGOpDef *def = &tcg_op_defs[op]; + return def->flags & TCG_OPF_64BIT ? 64 : 32; } static int op_to_movi(int op) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 2c7ca1a450..b48669b745 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -131,98 +131,98 @@ DEF(nor_i32, 1, 2, 0, 0) #endif #if TCG_TARGET_REG_BITS == 64 -DEF(mov_i64, 1, 1, 0, 0) -DEF(movi_i64, 1, 0, 1, 0) -DEF(setcond_i64, 1, 2, 1, 0) +DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT) +DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT) +DEF(setcond_i64, 1, 2, 1, TCG_OPF_64BIT) /* load/store */ -DEF(ld8u_i64, 1, 1, 1, 0) -DEF(ld8s_i64, 1, 1, 1, 0) -DEF(ld16u_i64, 1, 1, 1, 0) -DEF(ld16s_i64, 1, 1, 1, 0) -DEF(ld32u_i64, 1, 1, 1, 0) -DEF(ld32s_i64, 1, 1, 1, 0) -DEF(ld_i64, 1, 1, 1, 0) -DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) -DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) +DEF(ld8u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld8s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld16s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32u_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld32s_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(ld_i64, 1, 1, 1, TCG_OPF_64BIT) +DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) /* arith */ -DEF(add_i64, 1, 2, 0, 0) -DEF(sub_i64, 1, 2, 0, 0) -DEF(mul_i64, 1, 2, 0, 0) +DEF(add_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sub_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(mul_i64, 1, 2, 0, TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_div_i64 -DEF(div_i64, 1, 2, 0, 0) -DEF(divu_i64, 1, 2, 0, 0) -DEF(rem_i64, 1, 2, 0, 0) -DEF(remu_i64, 1, 2, 0, 0) +DEF(div_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(divu_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rem_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(remu_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_div2_i64 -DEF(div2_i64, 2, 3, 0, 0) -DEF(divu2_i64, 2, 3, 0, 0) +DEF(div2_i64, 2, 3, 0, TCG_OPF_64BIT) +DEF(divu2_i64, 2, 3, 0, TCG_OPF_64BIT) #endif -DEF(and_i64, 1, 2, 0, 0) -DEF(or_i64, 1, 2, 0, 0) -DEF(xor_i64, 1, 2, 0, 0) +DEF(and_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(or_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(xor_i64, 1, 2, 0, TCG_OPF_64BIT) /* shifts/rotates */ -DEF(shl_i64, 1, 2, 0, 0) -DEF(shr_i64, 1, 2, 0, 0) -DEF(sar_i64, 1, 2, 0, 0) +DEF(shl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(shr_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(sar_i64, 1, 2, 0, TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_rot_i64 -DEF(rotl_i64, 1, 2, 0, 0) -DEF(rotr_i64, 1, 2, 0, 0) +DEF(rotl_i64, 1, 2, 0, TCG_OPF_64BIT) +DEF(rotr_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_deposit_i64 -DEF(deposit_i64, 1, 2, 2, 0) +DEF(deposit_i64, 1, 2, 2, TCG_OPF_64BIT) #endif -DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) +DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) #ifdef TCG_TARGET_HAS_ext8s_i64 -DEF(ext8s_i64, 1, 1, 0, 0) +DEF(ext8s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext16s_i64 -DEF(ext16s_i64, 1, 1, 0, 0) +DEF(ext16s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext32s_i64 -DEF(ext32s_i64, 1, 1, 0, 0) +DEF(ext32s_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext8u_i64 -DEF(ext8u_i64, 1, 1, 0, 0) +DEF(ext8u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext16u_i64 -DEF(ext16u_i64, 1, 1, 0, 0) +DEF(ext16u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_ext32u_i64 -DEF(ext32u_i64, 1, 1, 0, 0) +DEF(ext32u_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap16_i64 -DEF(bswap16_i64, 1, 1, 0, 0) +DEF(bswap16_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap32_i64 -DEF(bswap32_i64, 1, 1, 0, 0) +DEF(bswap32_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_bswap64_i64 -DEF(bswap64_i64, 1, 1, 0, 0) +DEF(bswap64_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_not_i64 -DEF(not_i64, 1, 1, 0, 0) +DEF(not_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_neg_i64 -DEF(neg_i64, 1, 1, 0, 0) +DEF(neg_i64, 1, 1, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_andc_i64 -DEF(andc_i64, 1, 2, 0, 0) +DEF(andc_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_orc_i64 -DEF(orc_i64, 1, 2, 0, 0) +DEF(orc_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_eqv_i64 -DEF(eqv_i64, 1, 2, 0, 0) +DEF(eqv_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_nand_i64 -DEF(nand_i64, 1, 2, 0, 0) +DEF(nand_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #ifdef TCG_TARGET_HAS_nor_i64 -DEF(nor_i64, 1, 2, 0, 0) +DEF(nor_i64, 1, 2, 0, TCG_OPF_64BIT) #endif #endif @@ -68,7 +68,7 @@ static void tcg_target_qemu_prologue(TCGContext *s); static void patch_reloc(uint8_t *code_ptr, int type, tcg_target_long value, tcg_target_long addend); -static TCGOpDef tcg_op_defs[] = { +TCGOpDef tcg_op_defs[] = { #define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags }, #include "tcg-opc.h" #undef DEF @@ -445,13 +445,18 @@ typedef struct TCGArgConstraint { #define TCG_MAX_OP_ARGS 16 -#define TCG_OPF_BB_END 0x01 /* instruction defines the end of a basic - block */ -#define TCG_OPF_CALL_CLOBBER 0x02 /* instruction clobbers call registers - and potentially update globals. */ -#define TCG_OPF_SIDE_EFFECTS 0x04 /* instruction has side effects : it - cannot be removed if its output - are not used */ +/* Bits for TCGOpDef->flags, 8 bits available. */ +enum { + /* Instruction defines the end of a basic block. */ + TCG_OPF_BB_END = 0x01, + /* Instruction clobbers call registers and potentially update globals. */ + TCG_OPF_CALL_CLOBBER = 0x02, + /* Instruction has side effects: it cannot be removed + if its outputs are not used. */ + TCG_OPF_SIDE_EFFECTS = 0x04, + /* Instruction operands are 64-bits (otherwise 32-bits). */ + TCG_OPF_64BIT = 0x08, +}; typedef struct TCGOpDef { const char *name; @@ -463,6 +468,8 @@ typedef struct TCGOpDef { int used; #endif } TCGOpDef; + +extern TCGOpDef tcg_op_defs[]; typedef struct TCGTargetOpDef { TCGOpcode op; |