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authorRichard Henderson <richard.henderson@linaro.org>2019-07-09 10:40:00 +0200
committerRichard Henderson <richard.henderson@linaro.org>2019-07-14 12:19:00 +0200
commit359896dfa4e9707e1acea99129d324250fccab04 (patch)
treeda1df5ec403c4fcb42452ac9acd8c7853e143226
parent1789d4274b851fb8fdf4a947ce5474c63e813d0d (diff)
include/qemu/atomic.h: Add signal_barrier
We have some potential race conditions vs our user-exec signal handler that will be solved with this barrier. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--include/qemu/atomic.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index a6ac188188..f9cd24c899 100644
--- a/include/qemu/atomic.h
+++ b/include/qemu/atomic.h
@@ -88,6 +88,13 @@
#define smp_read_barrier_depends() barrier()
#endif
+/*
+ * A signal barrier forces all pending local memory ops to be observed before
+ * a SIGSEGV is delivered to the *same* thread. In practice this is exactly
+ * the same as barrier(), but since we have the correct builtin, use it.
+ */
+#define signal_barrier() __atomic_signal_fence(__ATOMIC_SEQ_CST)
+
/* Sanity check that the size of an atomic operation isn't "overly large".
* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
* want to use them because we ought not need them, and this lets us do a
@@ -308,6 +315,10 @@
#define smp_read_barrier_depends() barrier()
#endif
+#ifndef signal_barrier
+#define signal_barrier() barrier()
+#endif
+
/* These will only be atomic if the processor does the fetch or store
* in a single issue memory operation
*/