diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-06-16 11:03:19 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-27 13:48:21 +0200 |
| commit | 623e250abdca2c29830793e3ac81a9e405f33216 (patch) | |
| tree | 953162c9135dc0c65c72543e961ef880f50f63d8 | |
| parent | ff4873cb8c81db89668d8b56e19e57b852edb5f5 (diff) | |
linux-user: Correct AUXV Cache Line Sizes for PowerPC
Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the
CPU model's cache line sizes. This fixes memory clobbering problems on more
recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction
when N is sufficiently large and many of the newer server CPUs have cache lines
sizes of 128 bytes.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | linux-user/elfload.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1248eda272..64d23fa647 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -774,8 +774,9 @@ static uint32_t get_elf_hwcap(void) #define DLINFO_ARCH_ITEMS 5 #define ARCH_DLINFO \ do { \ - NEW_AUX_ENT(AT_DCACHEBSIZE, 0x20); \ - NEW_AUX_ENT(AT_ICACHEBSIZE, 0x20); \ + PowerPCCPU *cpu = POWERPC_CPU(thread_cpu); \ + NEW_AUX_ENT(AT_DCACHEBSIZE, cpu->env.dcache_line_size); \ + NEW_AUX_ENT(AT_ICACHEBSIZE, cpu->env.icache_line_size); \ NEW_AUX_ENT(AT_UCACHEBSIZE, 0); \ /* \ * Now handle glibc compatibility. \ |