diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2013-04-07 19:08:21 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-04-26 23:02:41 +0200 |
| commit | e03c902cb617414dae49d77a810f6957ff7affac (patch) | |
| tree | 89cfa89ace80401c09d4f6263f43f1ec97dc774e | |
| parent | 702763fa322ea69dde92517735507e0ac3879b5d (diff) | |
pseries: Fix some small errors in XICS logic
Under certain circumstances the emulation for the pseries "XICS" interrupt
controller was clearing a pending interrupt from the XISR register, without
also clearing the corresponding priority variable. This will cause
problems later when can trigger sanity checks in the under-development
in-kernel XICS implementation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | hw/ppc/xics.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/ppc/xics.c b/hw/ppc/xics.c index 8e1e85edfd..1b25075d14 100644 --- a/hw/ppc/xics.c +++ b/hw/ppc/xics.c @@ -101,6 +101,7 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr) if (XISR(ss) && (cppr <= ss->pending_priority)) { old_xisr = XISR(ss); ss->xirr &= ~XISR_MASK; /* Clear XISR */ + ss->pending_priority = 0xff; qemu_irq_lower(ss->output); ics_reject(icp->ics, old_xisr); } @@ -127,6 +128,7 @@ static uint32_t icp_accept(struct icp_server_state *ss) qemu_irq_lower(ss->output); ss->xirr = ss->pending_priority << 24; + ss->pending_priority = 0xff; trace_xics_icp_accept(xirr, ss->xirr); |