diff options
| author | Michael Clark <mjc@sifive.com> | 2018-04-30 11:06:31 +1200 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 1dc34be1c90b2d3006078d9d331e53a849cdecf3 (patch) | |
| tree | 7011d38f076ea00bb3ed9ec2fc711f03d953d1c1 | |
| parent | 6296a799b14142ccb813b678227ae9e6bf0ffa79 (diff) | |
RISC-V: Fix missing break statement in disassembler
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| -rw-r--r-- | disas/riscv.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index 2cecf0d855..7fd1019623 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) if (isa == rv128) { op = rv_op_c_sqsp; } else { - op = rv_op_c_fsdsp; break; + op = rv_op_c_fsdsp; } + break; case 6: op = rv_op_c_swsp; break; case 7: if (isa == rv32) { |