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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-29 19:54:32 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-29 19:54:32 +0000
commit5ef62c5c4224afdce2f98fb2c3b43f734ab47f72 (patch)
tree99bff6ca1f79271d78a0e9c4fa28a4193255c0a6
parent32af58f95f7b4e855f0369b25b46cbbbae69ae6c (diff)
More Sparc32 CPUs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2744 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-sparc/translate.c23
1 files changed, 20 insertions, 3 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 645b414228..4b8b3d261d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3355,11 +3355,28 @@ static const sparc_def_t sparc_defs[] = {
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
},
{
- /* XXX: Replace with real values */
+ .name = "Fujitsu MB86907",
+ .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
+ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
+ .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
+ },
+ {
+ .name = "TI MicroSparc I",
+ .iu_version = 0x41000000,
+ .fpu_version = 4 << 17,
+ .mmu_version = 0x41000000,
+ },
+ {
.name = "TI SuperSparc II",
.iu_version = 0x40000000,
- .fpu_version = 0x00000000,
- .mmu_version = 0x00000000,
+ .fpu_version = 0 << 17,
+ .mmu_version = 0x04000000,
+ },
+ {
+ .name = "Ross RT620",
+ .iu_version = 0x1e000000,
+ .fpu_version = 1 << 17,
+ .mmu_version = 0x17000000,
},
#endif
};